forked from OSchip/llvm-project
cfb6dfcbd1
Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing TruncInstCombine to reduce bitwidth of expressions containing these instructions. We should be shifting by less than the target bitwidth. Also it is sufficient to require that all truncated bits of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB Alive2 variable-length proof: https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia Part of https://reviews.llvm.org/D107766 Differential Revision: https://reviews.llvm.org/D108201 |
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| .. | ||
| AArch64 | ||
| ARM | ||
| X86 | ||
| 2010-03-22-empty-baseclass.ll | ||
| PR6627.ll | ||
| assume-explosion.ll | ||
| basic.ll | ||
| bitfield-bittests.ll | ||
| d83507-knowledge-retention-bug.ll | ||
| expect.ll | ||
| gdce.ll | ||
| globalaa-retained.ll | ||
| inlining-alignment-assumptions.ll | ||
| instcombine-sroa-inttoptr.ll | ||
| lifetime-sanitizer.ll | ||
| loop-rotation-vs-common-code-hoisting.ll | ||
| lto-licm.ll | ||
| min-max-abs-cse.ll | ||
| minmax.ll | ||
| openmp-opt-module.ll | ||
| partialord-ule.ll | ||
| pr32544.ll | ||
| pr36760.ll | ||
| pr39282.ll | ||
| pr44461-br-to-switch-rotate.ll | ||
| pr45682.ll | ||
| pr45687.ll | ||
| reassociate-after-unroll.ll | ||
| rotate.ll | ||
| scev-custom-dl.ll | ||
| scev.ll | ||
| simplifycfg-options.ll | ||
| two-shifts-by-sext.ll | ||
| unsigned-multiply-overflow-check.ll | ||
| vector-trunc-inseltpoison.ll | ||
| vector-trunc.ll | ||