Craig Topper 6bea2c7f9b [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. ... The %eiz/%riz are dummy registers that force the encoder to emit a SIB byte when it normally wouldn't. By emitting them in the disassembly output we ensure that assembling the disassembler output would also produce a SIB byte. This should match the behavior of objdump from binutils. llvm-svn: 335768		2018-06-27 19:03:36 +00:00
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AArch64	[AArch64] Fix spelling of ICH_ELRSR_EL2 system register	2018-02-06 09:39:04 +00:00
AMDGPU	AMDGPU: Fix v_dot{4, 8}* instruction encoding	2018-05-15 19:32:47 +00:00
ARC	[ARC] Add LImm support for J/JL	2018-04-13 15:10:34 +00:00
ARM	ARM: correctly decode VFP instructions following unpredictable t2IT	2018-06-26 11:39:20 +00:00
Hexagon	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
Lanai	…
Mips	[mips] Correct the predicates of arithmetic and logic instructions.	2018-05-30 11:33:35 +00:00
PowerPC	[PowerPC] Fix incorrectly encoded wait instruction	2018-06-25 19:28:27 +00:00
Sparc	…
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
WebAssembly	[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.	2018-06-18 21:22:44 +00:00
X86	[X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result.	2018-06-27 19:03:36 +00:00
XCore	…