forked from OSchip/llvm-project
90 lines
2.3 KiB
LLVM
90 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL
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; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: asr w0, w8, #3
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, 8
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ret i32 %div
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #7 // =7
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: neg w0, w8, asr #3
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, -8
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ret i32 %div
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #31 // =31
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: csel w8, w8, w0, lt
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; CHECK-NEXT: asr w0, w8, #5
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; CHECK-NEXT: ret
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%div = sdiv i32 %x, 32
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ret i32 %div
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}
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define i64 @test4(i64 %x) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #7 // =7
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #3
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 8
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ret i64 %div
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}
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define i64 @test5(i64 %x) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #7 // =7
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: neg x0, x8, asr #3
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, -8
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ret i64 %div
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}
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define i64 @test6(i64 %x) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #63 // =63
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #6
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 64
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ret i64 %div
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}
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define i64 @test7(i64 %x) {
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; CHECK-LABEL: test7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #281474976710655
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: cmp x0, #0 // =0
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; CHECK-NEXT: csel x8, x8, x0, lt
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; CHECK-NEXT: asr x0, x8, #48
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; CHECK-NEXT: ret
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%div = sdiv i64 %x, 281474976710656
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ret i64 %div
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}
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