forked from OSchip/llvm-project
121 lines
3.3 KiB
YAML
121 lines
3.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: shl_v2i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: shl_v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[USHLv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: shl_v4i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: shl_v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[USHLv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: ashr_v2i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: ashr_v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]]
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; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]]
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; CHECK: $d0 = COPY [[SSHLv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: ashr_v4i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: ashr_v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]
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; CHECK: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]]
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; CHECK: $q0 = COPY [[SSHLv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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