forked from OSchip/llvm-project
191 lines
6.5 KiB
YAML
191 lines
6.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define <4 x float> @test_f32(float %a, float %b, float %c, float %d) {
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ret <4 x float> undef
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}
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define <2 x double> @test_f64(double %a, double %b) {
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ret <2 x double> undef
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}
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define <4 x i32> @test_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
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ret <4 x i32> undef
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}
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define <2 x i64> @test_i64(i64 %a, i64 %b) {
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ret <2 x i64> undef
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}
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define void @test_p0(i64 *%a, i64 *%b) { ret void }
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...
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---
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name: test_f32
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $s0, $s1, $s2, $s3
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; CHECK-LABEL: name: test_f32
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; CHECK: liveins: $s0, $s1, $s2, $s3
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s3
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.ssub
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; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY2]], %subreg.ssub
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; CHECK: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0
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; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY3]], %subreg.ssub
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; CHECK: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0
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; CHECK: $q0 = COPY [[INSvi32lane2]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = COPY $s1
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%2:fpr(s32) = COPY $s2
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%3:fpr(s32) = COPY $s3
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%4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
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$q0 = COPY %4(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_f64
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $d0, $d1, $d2, $d3
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; CHECK-LABEL: name: test_f64
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; CHECK: liveins: $d0, $d1, $d2, $d3
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: $q0 = COPY [[INSvi64lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = COPY $d1
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%4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)
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$q0 = COPY %4(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_i32
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $w0, $w1, $w2, $w3
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; CHECK-LABEL: name: test_i32
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; CHECK: liveins: $w0, $w1, $w2, $w3
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
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; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
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; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY1]]
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; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, [[COPY2]]
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; CHECK: [[INSvi32gpr2:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, [[COPY3]]
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; CHECK: $q0 = COPY [[INSvi32gpr2]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = COPY $w2
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%3:gpr(s32) = COPY $w3
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%4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
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$q0 = COPY %4(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_i64
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_i64
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
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; CHECK: $q0 = COPY [[INSvi64gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)
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$q0 = COPY %4(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_p0
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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failedISel: false
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $x0, $x1
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; CHECK-LABEL: name: test_p0
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
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; CHECK: $q0 = COPY [[INSvi64gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(p0) = COPY $x0
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%1:gpr(p0) = COPY $x1
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%4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
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$q0 = COPY %4(<2 x p0>)
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RET_ReallyLR implicit $q0
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...
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