forked from OSchip/llvm-project
228 lines
6.6 KiB
YAML
228 lines
6.6 KiB
YAML
# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: test_v4f16.log2
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.log2
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; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
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; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
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; CHECK-NEXT: BL &log2
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; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
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; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
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; CHECK-NEXT: BL &log2
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; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
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; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
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; CHECK-NEXT: BL &log2
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; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
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; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
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; CHECK-NEXT: BL &log2
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; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
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; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_FLOG2 %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.log2
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.log2
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; This is big, so let's just check for the 8 calls to log2, the the
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; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought
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; to be covered by the other tests.
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; CHECK: G_UNMERGE_VALUES
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: BL &log2
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; CHECK-DAG: G_BUILD_VECTOR
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_FLOG2 %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.log2
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.log2
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; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V1]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V2]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_FLOG2 %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.log2
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.log2
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; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V1]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V2]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V3]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $s0 = COPY [[V4]](s32)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32)
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_FLOG2 %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.log2
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.log2
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; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-DAG: $d0 = COPY [[V1]](s64)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: ADJCALLSTACKDOWN
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; CHECK-DAG: $d0 = COPY [[V2]](s64)
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; CHECK-DAG: BL &log2
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; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK-DAG: ADJCALLSTACKUP
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; CHECK-DAG: %1:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64)
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = G_FLOG2 %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_log2_half
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_log2_half
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; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
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; CHECK-NEXT: ADJCALLSTACKDOWN
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; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
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; CHECK-NEXT: BL &log2
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; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-NEXT: ADJCALLSTACKUP
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; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_FLOG2 %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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