llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_combines_2() { ret void }
define void @test_combines_3() { ret void }
define void @test_combines_4() { ret void }
define void @test_combines_5() { ret void }
define void @test_combines_6() { ret void }
...
---
name: test_combines_2
body: |
bb.0:
liveins: $w0
; Here the types don't match.
; CHECK-LABEL: name: test_combines_2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[COPY]](s32), 0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s1)
; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s1) = G_EXTRACT %2, 0
%5:_(s32) = G_ANYEXT %3
$w0 = COPY %5
%4:_(s64) = COPY %2
$x0 = COPY %4
...
---
name: test_combines_3
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: test_combines_3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
; CHECK: $w0 = COPY [[ADD1]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ADD %3, %4
$w0 = COPY %5
...
---
name: test_combines_4
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: test_combines_4
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
; CHECK: $x0 = COPY [[ADD]](s64)
%0:_(s64) = COPY $x0
%1:_(s128) = G_MERGE_VALUES %0, %0
%2:_(s64) = G_EXTRACT %1, 0
%3:_(s64) = G_ADD %2, %2
$x0 = COPY %3
...
---
name: test_combines_5
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: test_combines_5
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
; CHECK: $w0 = COPY [[ADD1]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%6:_(s64) = COPY %2
%7:_(s64) = COPY %6
%8:_(s64) = COPY %7
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %8
%5:_(s32) = G_ADD %3, %4
$w0 = COPY %5
...
---
name: test_combines_6
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: test_combines_6
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
; CHECK: $w0 = COPY [[ADD1]](s32)
; CHECK: $x0 = COPY [[COPY2]](s64)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%6:_(s64) = COPY %2
%7:_(s64) = COPY %6
%8:_(s64) = COPY %7
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %8
%5:_(s32) = G_ADD %3, %4
$w0 = COPY %5
$x0 = COPY %7
...