Andrea Di Biagio 561badf717 Fix edge condition in DAGCombiner to improve codegen of shift sequences. ... When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. llvm-svn: 192883		2013-10-17 11:02:58 +00:00
clang	Remove unicode characters, trailing whitespace from test case	2013-10-17 09:55:56 +00:00
clang-tools-extra	Added module map generation docs and some clean-up.	2013-10-16 13:44:21 +00:00
compiler-rt	[Sanitizer] Move pthread_cond_signal and pthread_cond_broadcast to common interceptors	2013-10-17 09:24:03 +00:00
debuginfo-tests	don't use CHECK-NEXT because it may be on the same line.	2013-09-18 23:01:54 +00:00
libclc	Port pocl's gen_convert.py script to libclc	2013-10-10 19:09:01 +00:00
libcxx	r192075 broke the buildbot at	2013-10-14 18:02:02 +00:00
libcxxabi	unwinder: conditionalise availability	2013-10-17 03:57:41 +00:00
lld	Make undefines check into an assertion.	2013-10-16 19:21:50 +00:00
lldb	<rdar://problem/14972424>	2013-10-17 01:10:23 +00:00
llvm	Fix edge condition in DAGCombiner to improve codegen of shift sequences.	2013-10-17 11:02:58 +00:00
openmp	Update web pages to include style sheets and referenced documents missed before.	2013-10-03 11:55:28 +00:00
polly	clang-format: No empty line after 'public:'	2013-10-15 14:41:02 +00:00