llvm-project/llvm/test/CodeGen/MIR/PowerPC
Zaara Syeda 5c179bf14b [Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.

Differential Revision: https://reviews.llvm.org/D39386

llvm-svn: 346512
2018-11-09 16:36:24 +00:00
..
ifcvt-diamond-ret.mir
lit.local.cfg
prolog_vec_spills.mir [Power9] Allow gpr callee saved spills in prologue to vectors registers 2018-11-09 16:36:24 +00:00
unordered-implicit-registers.mir