llvm-project/llvm/test/CodeGen/AVR/pseudo
Dylan McKay 9a9ae99b30 [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination
This is an AVR-specific workaround for a limitation of the register
allocator that only exposes itself on targets with high register
contention like AVR, which only has three pointer registers.

The three pointer registers are X, Y, and Z.
In most nontrivial functions, Y is reserved for the frame pointer,
as per the calling convention. This leaves X and Z. Some instructions,
such as LPM ("load program memory"), are only defined for the Z
register. Sometimes this just leaves X.

When the backend generates a LDDWRdPtrQ instruction with Z as the
destination pointer, it usually trips up the register allocator
with this error message:

  LLVM ERROR: ran out of registers during register allocation

This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction
from ever using the Z register as an operand. This gives the
register allocator a bit more space to allocate, fixing the
regalloc exhaustion error.

Here is a description from the patch author Peter Nimmervoll

  As far as I understand the problem occurs when LDDWRdPtrQ uses
  the ptrdispregs register class as target register. This should work, but
  the allocator can't deal with this for some reason. So from my testing,
  it seams like (and I might be totally wrong on this) the allocator reserves
  the Z register for the ICALL instruction and then the register class
  ptrdispregs only has 1 register left and we can't use Y for source and
  destination. Removing the Z register from DREGS fixes the problem but
  removing Y register does not.

More information about the bug can be found on the avr-rust issue
tracker at https://github.com/avr-rust/rust/issues/37.

A bug has raised to track the removal of this workaround and a proper
fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553.

Patch by Peter Nimmervoll

llvm-svn: 346114
2018-11-05 05:00:44 +00:00
..
ADCWRdRr.mir
ADDWRdRr.mir
ANDIWRdK.mir
ANDWRdRr.mir
ASRWRd.mir
COMWRd.mir
CPCWRdRr.mir
CPWRdRr.mir
EORWRdRr.mir
FRMIDX.mir
INWRdA.mir
LDDWRdPtrQ-same-src-dst.mir [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination 2018-11-05 05:00:44 +00:00
LDDWRdPtrQ.mir [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination 2018-11-05 05:00:44 +00:00
LDDWRdYQ.mir
LDIWRdK.mir
LDSWRdK.mir
LDWRdPtr-same-src-dst.mir
LDWRdPtr.mir
LDWRdPtrPd.mir
LDWRdPtrPi.mir
LSLWRd.mir [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
LSRWRd.mir
ORIWRdK.mir
ORWRdRr.mir
OUTWARr.mir
POPWRd.mir
PUSHWRr.mir
SBCIWRdK.mir
SBCWRdRr.mir
SEXT.mir [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
STDWPtrQRr.mir
STSWKRr.mir
STWPtrPdRr.mir
STWPtrPiRr.mir
STWPtrRr.mir
SUBIWRdK.mir
SUBWRdRr.mir
ZEXT.mir [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00