llvm-project/llvm/lib/Target/Sparc
Chris Dewhurst 053826af69 The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.

Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.

llvm-svn: 262133
2016-02-27 12:49:59 +00:00
..
AsmParser The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
Disassembler The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
InstPrinter Remove autoconf support 2016-01-26 21:29:08 +00:00
MCTargetDesc Remove autoconf support 2016-01-26 21:29:08 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
CMakeLists.txt Remove getDataLayout() from TargetSelectionDAGInfo (had no users) 2015-07-09 02:10:08 +00:00
DelaySlotFiller.cpp Add a TODO item that the nop handling before FP conditional branches is 2015-12-03 02:35:24 +00:00
LLVMBuild.txt
README.txt Initial test commit only 2016-02-26 11:38:24 +00:00
Sparc.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
Sparc.td [SparcInstPrinter] Use the subtarget that is passed to the print function 2015-03-28 04:03:51 +00:00
SparcAsmPrinter.cpp Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 2016-02-22 20:49:58 +00:00
SparcCallingConv.td [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SparcFrameLowering.cpp Update to use new name alignTo(). 2016-01-14 21:06:47 +00:00
SparcFrameLowering.h [SPARC] Fix stupid oversight in stack realignment support. 2015-08-26 17:57:51 +00:00
SparcISelDAGToDAG.cpp [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SparcISelLowering.cpp Fix Sparc 32bit Lowering to rebundle up v2i32 values. 2016-02-26 18:55:22 +00:00
SparcISelLowering.h [WinEH] Update exception pointer registers 2015-11-07 01:11:31 +00:00
SparcInstr64Bit.td Sparc: Add the "alternate address space" load/store instructions. 2015-05-18 16:35:04 +00:00
SparcInstrAliases.td [SPARC] Repair floating-point condition encodings in assembly parser. 2016-02-10 17:47:20 +00:00
SparcInstrFormats.td Sparc: support the "set" synthetic instruction. 2015-05-18 16:43:33 +00:00
SparcInstrInfo.cpp CodeGen: TII: Take MachineInstr& in predicate API, NFC 2016-02-23 02:46:52 +00:00
SparcInstrInfo.h [SPARC] Revamp AnalyzeBranch and add ReverseBranchCondition. 2016-01-13 04:44:14 +00:00
SparcInstrInfo.td The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
SparcInstrVIS.td
SparcMCInstLower.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
SparcRegisterInfo.cpp [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.h [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.td The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
SparcSubtarget.cpp Update to use new name alignTo(). 2016-01-14 21:06:47 +00:00
SparcSubtarget.h Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/ 2016-01-27 16:32:26 +00:00
SparcTargetMachine.cpp Replace string GNU Triples with llvm::Triple in TargetMachine. NFC. 2015-06-11 19:41:26 +00:00
SparcTargetMachine.h Replace string GNU Triples with llvm::Triple in TargetMachine. NFC. 2015-06-11 19:41:26 +00:00
SparcTargetObjectFile.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
SparcTargetObjectFile.h
SparcTargetStreamer.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.