forked from OSchip/llvm-project
125 lines
3.2 KiB
LLVM
125 lines
3.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure we don't crash or assert on spir_kernel calling convention.
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; GCN-LABEL: {{^}}kernel:
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; GCN: s_endpgm
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define spir_kernel void @kernel(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This is treated like a kernel
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; XGCN-LABEL: {{^}}func:
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; XGCN: s_endpgm
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; define spir_func void @func(i32 addrspace(1)* %out) {
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; entry:
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; store i32 0, i32 addrspace(1)* %out
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; ret void
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; }
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; GCN-LABEL: {{^}}ps_ret_cc_f16:
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; SI: v_cvt_f16_f32_e32 v0, v0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e32 v0, 1.0, v0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16:
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; SI: v_cvt_f16_f32_e32 v0, s0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e64 v0, s0, 1.0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; GCN-LABEL: {{^}}fastcc:
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; GCN: v_add_f32_e32 v0, 4.0, v0
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define fastcc float @fastcc(float %arg0) #0 {
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%add = fadd float %arg0, 4.0
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ret float %add
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}
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; GCN-LABEL: {{^}}coldcc:
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; GCN: v_add_f32_e32 v0, 4.0, v0
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define coldcc float @coldcc(float %arg0) #0 {
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%add = fadd float %arg0, 4.0
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ret float %add
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}
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; GCN-LABEL: {{^}}call_coldcc:
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; GCN: v_mov_b32_e32 v0, 1.0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @call_coldcc() #0 {
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%val = call float @coldcc(float 1.0)
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store float %val, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}call_fastcc:
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; GCN: v_mov_b32_e32 v0, 1.0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @call_fastcc() #0 {
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%val = call float @fastcc(float 1.0)
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store float %val, float addrspace(1)* undef
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ret void
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}
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; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 47176
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; GCN-LABEL: {{^}}cs_mesa:
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define amdgpu_cs half @cs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45096
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; GCN-LABEL: {{^}}ps_mesa:
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define amdgpu_ps half @ps_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45352
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; GCN-LABEL: {{^}}vs_mesa:
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define amdgpu_vs half @vs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45608
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; GCN-LABEL: {{^}}gs_mesa:
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define amdgpu_gs half @gs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 46120
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; GCN-LABEL: {{^}}hs_mesa:
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define amdgpu_hs half @hs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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attributes #0 = { nounwind noinline }
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