llvm-project/llvm/test/CodeGen
Saleem Abdulrasool fe83b50289 ARM: address WoA division limitation
We now emit the compiler generated divide by zero check that was needed for the
MSVC routines.  We construct a psuedo-instruction for the DBZ check as the
operation requires splitting up the BB.  For the 64-bit operations, we need to
custom expand the node as we need to insert the DBZ check and then emit the
libcall to the appropriate name.  Because this is target specific, it seemed
better to reproduce the expansion operation from the target-agnostic type
legalization rather than sink this there to avoid the duplication.  The division
library calls now match MSVC semantically.

llvm-svn: 248561
2015-09-25 05:15:46 +00:00
..
AArch64 Swap loop invariant GEP with loop variant GEP to allow more LICM. 2015-09-23 19:25:30 +00:00
AMDGPU AMDGPU: Add s_dcache_* instructions 2015-09-24 19:52:27 +00:00
ARM ARM: address WoA division limitation 2015-09-25 05:15:46 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP Fix CPP Backend for GEP API changes for opaque pointer types 2015-09-08 18:42:29 +00:00
Generic Make the default triple optional by allowing an empty string 2015-09-16 05:34:32 +00:00
Hexagon Update edge weights properly when merging blocks in if-conversion. 2015-09-18 20:22:41 +00:00
Inputs DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
MIR Fix PR 24724 - The implicit register verifier shouldn't assume certain operand 2015-09-10 14:04:34 +00:00
MSP430
Mips [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00
NVPTX [NVPTX] Let NVPTX backend detect integer min and max patterns. 2015-08-26 23:22:02 +00:00
PowerPC DAGCombiner: Replace store of FP constant after attemping store merges 2015-09-21 15:59:46 +00:00
SPARC [SPARC] Switch to the Machine Scheduler. 2015-09-10 21:49:06 +00:00
SystemZ [SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOS 2015-09-21 17:35:45 +00:00
Thumb DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
Thumb2 Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are scaled by a probability to avoid precision issue. 2015-09-18 18:19:40 +00:00
WebAssembly [WebAssembly] Check in an initial CFG Stackifier pass 2015-09-16 16:51:30 +00:00
WinEH [WinEH] Rip out the landingpad-based C++ EH state numbering code 2015-09-16 22:14:46 +00:00
X86 [X86][SSE2] Fix zero/any extension shuffles that don't start from the first element 2015-09-24 21:02:17 +00:00
XCore [opaque pointer type] Add textual IR support for explicit type parameter for global aliases 2015-09-11 03:22:04 +00:00