llvm-project/llvm/test/CodeGen
Nikita Popov 835104a114 [LSR] Drop potentially invalid nowrap flags when switching to post-inc IV (PR46943)
When LSR converts a branch on the pre-inc IV into a branch on the
post-inc IV, the nowrap flags on the addition may no longer be valid.
Previously, a poison result of the addition might have been ignored,
in which case the program was well defined. After branching on the
post-inc IV, we might be branching on poison, which is undefined behavior.

Fix this by discarding nowrap flags which are not present on the SCEV
expression. Nowrap flags on the SCEV expression are proven by SCEV
to always hold, independently of how the expression will be used.
This is essentially the same fix we applied to IndVars LFTR, which
also performs this kind of pre-inc to post-inc conversion.

I believe a similar problem can also exist for getelementptr inbounds,
but I was not able to come up with a problematic test case. The
inbounds case would have to be addressed in a differently anyway
(as SCEV does not track this property).

Fixes https://bugs.llvm.org/show_bug.cgi?id=46943.

Differential Revision: https://reviews.llvm.org/D95286
2021-01-25 23:13:48 +01:00
..
AArch64 Recommit "[AArch64][GlobalISel] Implement widenScalar for signed overflow" 2021-01-25 16:57:20 -05:00
AMDGPU Revert "[IndirectFunctions] Skip propagating attributes to address taken functions" 2021-01-25 15:58:06 -05:00
ARC
ARM [ARM] Disable sign extended SSAT pattern recognition. 2021-01-22 14:07:48 +00:00
AVR [AVR] Optimize 8-bit int shift 2021-01-24 11:04:37 +08:00
BPF
Generic Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
Hexagon [NewPM][opt] Run the "default" AA pipeline by default 2021-01-21 21:08:54 -08:00
Inputs
Lanai
MIR [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
MSP430
Mips [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
NVPTX [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
PowerPC [PowerPC] Add missing negate for VPERMXOR on little endian subtargets 2021-01-25 12:23:33 -06:00
RISCV [RISCV] Add RVV insertelt/extractelt scalable-vector patterns 2021-01-25 22:03:52 +00:00
SPARC [SPARC] Fix fp128 load/stores 2021-01-13 14:59:50 -08:00
SystemZ [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds 2021-01-14 15:46:27 +00:00
Thumb [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer 2021-01-23 09:10:03 +00:00
Thumb2 [LSR] Drop potentially invalid nowrap flags when switching to post-inc IV (PR46943) 2021-01-25 23:13:48 +01:00
VE [VE] Update VELIntrinsic tests 2021-01-13 00:12:50 +09:00
WebAssembly [WebAssembly] Prototype new f64x2 conversions 2021-01-20 11:28:06 -08:00
WinCFGuard
WinEH
X86 [Win64] Ensure all stack frames are 8 byte aligned 2021-01-25 10:39:27 -08:00
XCore [test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:47:16 -08:00