forked from OSchip/llvm-project
188 lines
6.8 KiB
C++
188 lines
6.8 KiB
C++
//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "This shouldn't be built without GISel"
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#endif
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {
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}
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bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
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assert(MIB.getInstr() && "Unable to build a return instruction?!");
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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if (VReg) {
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MIRBuilder.setInstr(*MIB.getInstr(), /* Before */ true);
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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handleAssignments(
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MIRBuilder, AssignFn, MVT::getVT(Val->getType()), VReg,
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[&](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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});
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}
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return true;
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}
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bool AArch64CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
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CCAssignFn *AssignFn,
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ArrayRef<MVT> ArgTypes,
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ArrayRef<unsigned> ArgRegs,
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AssignFnTy AssignValToReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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unsigned NumArgs = ArgTypes.size();
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auto CurVT = ArgTypes.begin();
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for (unsigned i = 0; i != NumArgs; ++i, ++CurVT) {
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bool Res = AssignFn(i, *CurVT, *CurVT, CCValAssign::Full, ISD::ArgFlagsTy(),
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CCInfo);
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assert(!Res && "Call operand has unhandled type");
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(void)Res;
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}
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assert(ArgLocs.size() == ArgTypes.size() &&
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"We have a different number of location and args?!");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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assert(VA.isRegLoc() && "Not yet implemented");
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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// We don't care about bitcast.
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break;
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case CCValAssign::AExt:
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// Existing high bits are fine for anyext (whatever they are).
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break;
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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// Zero/Sign extend the register.
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assert(0 && "Not yet implemented");
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break;
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}
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// Everything checks out, tell the caller where we've decided this
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// parameter/return value should go.
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AssignValToReg(MIRBuilder, ArgRegs[i], VA.getLocReg());
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}
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return true;
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}
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bool AArch64CallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args,
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ArrayRef<unsigned> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<MVT, 8> ArgTys;
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for (auto &Arg : Args)
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ArgTys.push_back(MVT::getVT(Arg.getType()));
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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return handleAssignments(
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MIRBuilder, AssignFn, ArgTys, VRegs,
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[](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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MIRBuilder.buildCopy(ValReg, PhysReg);
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});
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}
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bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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const CallInst &CI, unsigned CalleeReg,
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unsigned ResReg,
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ArrayRef<unsigned> ArgRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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// First step is to marshall all the function's parameters into the correct
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// physregs and memory locations. Gather the sequence of argument types that
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// we'll pass to the assigner function.
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SmallVector<MVT, 8> ArgTys;
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for (auto &Arg : CI.arg_operands())
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ArgTys.push_back(MVT::getVT(Arg->getType()));
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// Find out which ABI gets to decide where things go.
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *CallAssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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// And finally we can do the actual assignments. For a call we need to keep
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// track of the registers used because they'll be implicit uses of the BL.
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SmallVector<unsigned, 8> PhysRegs;
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handleAssignments(
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MIRBuilder, CallAssignFn, ArgTys, ArgRegs,
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[&](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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PhysRegs.push_back(PhysReg);
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});
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// Now we can build the actual call instruction.
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MachineInstrBuilder MIB;
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if (CalleeReg)
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MIB = MIRBuilder.buildInstr(AArch64::BLR).addUse(CalleeReg);
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else
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MIB = MIRBuilder.buildInstr(AArch64::BL)
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.addGlobalAddress(CI.getCalledFunction());
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// Tell the call which registers are clobbered.
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auto TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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for (auto Reg : PhysRegs)
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MIB.addUse(Reg, RegState::Implicit);
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// Finally we can copy the returned value back into its virtual-register. In
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// symmetry with the arugments, the physical register must be an
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// implicit-define of the call instruction.
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CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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if (!CI.getType()->isVoidTy())
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handleAssignments(
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MIRBuilder, RetAssignFn, MVT::getVT(CI.getType()), ResReg,
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[&](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(ValReg, PhysReg);
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MIB.addDef(PhysReg, RegState::Implicit);
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});
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return true;
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}
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