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llvm-project/llvm/lib/Target/AArch64
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Matt Arsenault 567631bdd4 BranchRelaxation: Fix handling of blocks with multiple conditional 
branches

Looping over all terminators exposed AArch64 tests hitting
an assert from analyzeBranch failing. I believe these cases
were miscompiled before.

e.g.
  fcmp s0, s1
  b.ne LBB0_1
  b.vc LBB0_2
  b LBB0_2
LBB0_1:
  ; Large block
LBB0_2:
 ; ...

Both of the individual conditional branches need to
be expanded, since neither can reach the final block.

Split the original block into ones which analyzeBranch
will be able to understand.

llvm-svn: 279499
 		2016-08-23 01:30:30 +00:00
..
AsmParser AArch64: remove extraneous padding 2016-08-18 22:35:06 +00:00
Disassembler Replace "fallthrough" comments with LLVM_FALLTHROUGH 2016-08-17 05:10:15 +00:00
InstPrinter AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
MCTargetDesc [AArch64] Registering default MCInstrAnalysis 2016-08-12 20:28:05 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils AArch64: try to fix optimized build failure. 2016-07-05 23:15:58 +00:00
AArch64.h [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64.td [AArch64] Add support for Samsung Exynos M2 (NFC). 2016-08-01 18:39:45 +00:00
AArch64A53Fix835769.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64A57FPLoadBalancing.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64AddressTypePromotion.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64AdvSIMDScalarPass.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64AsmPrinter.cpp AArch64: Change modeling of zero cycle zeroing. 2016-07-06 21:39:33 +00:00
AArch64BranchRelaxation.cpp BranchRelaxation: Fix handling of blocks with multiple conditional 2016-08-23 01:30:30 +00:00
AArch64CallLowering.cpp GlobalISel: implement simple function calls on AArch64. 2016-08-10 21:44:01 +00:00
AArch64CallLowering.h Fixed VS2015 (Update 3) warning - differing const/volatile qualifiers for overridden function 2016-08-11 12:19:43 +00:00
AArch64CallingConvention.h Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. 2015-12-05 07:13:35 +00:00
AArch64CallingConvention.td GlobalISel[AArch64]: support pointer types in argument lowering. 2016-07-25 21:01:17 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64CollectLOH.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64ConditionOptimizer.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64ConditionalCompares.cpp Replace a few more "fall through" comments with LLVM_FALLTHROUGH 2016-08-17 20:30:52 +00:00
AArch64DeadRegisterDefinitionsPass.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pass. NFCI. 2016-07-20 21:45:58 +00:00
AArch64FastISel.cpp AArch64: properly calculate cmpxchg status in FastISel. 2016-08-02 20:22:36 +00:00
AArch64FrameLowering.cpp Move helpers into anonymous namespaces. NFC. 2016-08-06 11:13:10 +00:00
AArch64FrameLowering.h [PEI, AArch64] Use empty spaces in stack area for local stack slot allocation. 2016-06-02 16:22:07 +00:00
AArch64ISelDAGToDAG.cpp Use the range variant of transform instead of unpacking begin/end 2016-08-12 04:32:42 +00:00
AArch64ISelLowering.cpp Replace a few more "fall through" comments with LLVM_FALLTHROUGH 2016-08-17 20:30:52 +00:00
AArch64ISelLowering.h GlobalISel: implement simple function calls on AArch64. 2016-08-10 21:44:01 +00:00
AArch64InstrAtomics.td AArch64: properly calculate cmpxchg status in FastISel. 2016-08-02 20:22:36 +00:00
AArch64InstrFormats.td [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround 2016-08-18 20:08:15 +00:00
AArch64InstrInfo.cpp Replace "fallthrough" comments with LLVM_FALLTHROUGH 2016-08-17 05:10:15 +00:00
AArch64InstrInfo.h [AArch64] Re-factor code shared by AArch64LoadStoreOpt and AArch64InstrInfo. 2016-08-12 15:26:00 +00:00
AArch64InstrInfo.td [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround 2016-08-18 20:08:15 +00:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] Select floating-point binary ops. 2016-08-18 16:05:11 +00:00
AArch64InstructionSelector.h [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
AArch64LoadStoreOptimizer.cpp [AArch64LoadStoreOptimizer] Check aliasing correctly when creating paired loads/stores. 2016-08-12 20:39:51 +00:00
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
…
AArch64MachineFunctionInfo.h [AArch64] Mark various *Info classes as 'final'. NFC. 2016-07-27 14:31:46 +00:00
AArch64MachineLegalizer.cpp GlobalISel: support legalization of G_FCONSTANTs 2016-08-19 22:40:08 +00:00
AArch64MachineLegalizer.h Fix include case. NFC. 2016-07-22 20:15:19 +00:00
AArch64PBQPRegAlloc.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64RedundantCopyElimination.cpp AArch64: Don't call getIterator() on iterators 2016-08-18 17:58:09 +00:00
AArch64RegisterBankInfo.cpp GlobalISel: implement low-level type with just size & vector lanes. 2016-07-20 19:09:30 +00:00
AArch64RegisterBankInfo.h [AArch64] Mark various *Info classes as 'final'. NFC. 2016-07-27 14:31:46 +00:00
AArch64RegisterInfo.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
AArch64RegisterInfo.h [AArch64] Mark various *Info classes as 'final'. NFC. 2016-07-27 14:31:46 +00:00
AArch64RegisterInfo.td Fix typo in comment. NFC 2016-04-24 17:55:57 +00:00
AArch64SchedA53.td Remove MinLatency in SchedMachineModel. NFC. 2016-04-26 00:37:46 +00:00
AArch64SchedA57.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64SchedKryo.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedKryoDetails.td [AArch64] Add support for Qualcomm Kryo CPU. 2016-02-12 15:51:51 +00:00
AArch64SchedM1.td [AArch64] Adjust the scheduling model for Exynos M1. 2016-08-16 20:35:01 +00:00
AArch64SchedVulcan.td [AArch64] Add Broadcom Vulcan scheduling model. 2016-06-30 06:42:31 +00:00
AArch64Schedule.td CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64SelectionDAGInfo.cpp [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCallee 2016-06-22 12:54:25 +00:00
AArch64SelectionDAGInfo.h Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
AArch64StorePairSuppress.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64Subtarget.cpp [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
AArch64Subtarget.h [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
AArch64SystemOperands.td AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
AArch64TargetMachine.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64TargetMachine.h Delete Reloc::Default. 2016-05-18 22:04:49 +00:00
AArch64TargetObjectFile.cpp
…
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp AArch64: Do not test for CPUs, use SubtargetFeatures 2016-06-02 18:03:53 +00:00
AArch64TargetTransformInfo.h [TTI] Add hook for vector extract with extension 2016-04-27 15:20:21 +00:00
CMakeLists.txt [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
LLVMBuild.txt [AArch64] Plug the beginning of the GlobalISel pipeline. 2016-02-11 19:35:06 +00:00