forked from OSchip/llvm-project
153 lines
5.5 KiB
C++
153 lines
5.5 KiB
C++
//==- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass -*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// Hexagon target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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#include "Hexagon.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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namespace llvm {
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class Loop;
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class ScalarEvolution;
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class User;
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class Value;
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class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
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using BaseT = BasicTTIImplBase<HexagonTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const HexagonSubtarget &ST;
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const HexagonTargetLowering &TLI;
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const HexagonSubtarget *getST() const { return &ST; }
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const HexagonTargetLowering *getTLI() const { return &TLI; }
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bool useHVX() const;
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bool isTypeForHVX(Type *VecTy) const;
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// Returns the number of vector elements of Ty, if Ty is a vector type,
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// or 1 if Ty is a scalar type. It is incorrect to call this function
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// with any other type.
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unsigned getTypeNumElements(Type *Ty) const;
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public:
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explicit HexagonTTIImpl(const HexagonTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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ST(*TM->getSubtargetImpl(F)), TLI(*ST.getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
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// The Hexagon target can unroll loops with run-time trip counts.
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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/// Bias LSR towards creating post-increment opportunities.
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bool shouldFavorPostInc() const;
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// L1 cache prefetch.
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unsigned getPrefetchDistance() const;
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unsigned getCacheLineSize() const;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool vector) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getMinimumVF(unsigned ElemWidth) const;
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bool shouldMaximizeVectorBandwidth(bool OptSize) const {
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return true;
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}
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bool supportsEfficientVectorElementLoadStore() {
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return false;
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}
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bool hasBranchDivergence() {
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return false;
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}
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bool enableAggressiveInterleaving(bool LoopHasReductions) {
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return false;
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}
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bool prefersVectorizedAddressing() {
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return false;
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}
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bool enableInterleavedAccessVectorization() {
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return true;
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}
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
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unsigned getOperandsScalarizationOverhead(ArrayRef<const Value*> Args,
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unsigned VF);
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unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type*> Tys);
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF);
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type*> Tys, FastMathFlags FMF,
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unsigned ScalarizationCostPassed = UINT_MAX);
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unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *SE,
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const SCEV *S);
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace, const Instruction *I = nullptr);
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unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace);
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unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp);
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unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
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bool VariableMask, unsigned Alignment);
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unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment,
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unsigned AddressSpace, bool UseMaskForCond = false,
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bool UseMaskForGaps = false);
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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const Instruction *I);
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unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I = nullptr);
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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unsigned getCFInstrCost(unsigned Opcode) {
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return 1;
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}
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/// @}
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int getUserCost(const User *U, ArrayRef<const Value *> Operands);
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// Hexagon specific decision to generate a lookup table.
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bool shouldBuildLookupTables() const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H
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