forked from OSchip/llvm-project
653 lines
24 KiB
TableGen
653 lines
24 KiB
TableGen
//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "RISCVInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
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def SDT_RISCVCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
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SDTCisVT<1, i32>]>;
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def SDT_RISCVCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
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SDTCisVT<1, i32>]>;
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def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
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SDTCisSameAs<0, 4>,
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SDTCisSameAs<4, 5>]>;
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def Call : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def SelectCC : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
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[SDNPInGlue]>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
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let Name = prefix # "Imm" # width # suffix;
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let RenderMethod = "addImmOperands";
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let DiagnosticType = !strconcat("Invalid", Name);
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}
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class SImmAsmOperand<int width, string suffix = "">
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: ImmAsmOperand<"S", width, suffix> {
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}
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class UImmAsmOperand<int width, string suffix = "">
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: ImmAsmOperand<"U", width, suffix> {
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}
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def FenceArg : AsmOperandClass {
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let Name = "FenceArg";
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let RenderMethod = "addFenceArgOperands";
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let DiagnosticType = "InvalidFenceArg";
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}
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def fencearg : Operand<XLenVT> {
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let ParserMatchClass = FenceArg;
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let PrintMethod = "printFenceArg";
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let DecoderMethod = "decodeUImmOperand<4>";
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}
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def UImmLog2XLenAsmOperand : AsmOperandClass {
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let Name = "UImmLog2XLen";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = "InvalidUImmLog2XLen";
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}
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def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
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if (Subtarget->is64Bit())
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return isUInt<6>(Imm);
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return isUInt<5>(Imm);
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}]> {
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let ParserMatchClass = UImmLog2XLenAsmOperand;
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// TODO: should ensure invalid shamt is rejected when decoding.
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let DecoderMethod = "decodeUImmOperand<6>";
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}
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def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<5>;
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let DecoderMethod = "decodeUImmOperand<5>";
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}
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def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<12>;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeSImmOperand<12>";
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}
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def uimm12 : Operand<XLenVT> {
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let ParserMatchClass = UImmAsmOperand<12>;
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let DecoderMethod = "decodeUImmOperand<12>";
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}
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// A 13-bit signed immediate where the least significant bit is zero.
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def simm13_lsb0 : Operand<OtherVT> {
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let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
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let EncoderMethod = "getImmOpValueAsr1";
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let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
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}
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def uimm20 : Operand<XLenVT> {
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let ParserMatchClass = UImmAsmOperand<20>;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<20>";
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}
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// A 21-bit signed immediate where the least significant bit is zero.
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def simm21_lsb0 : Operand<OtherVT> {
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let ParserMatchClass = SImmAsmOperand<21, "Lsb0">;
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let EncoderMethod = "getImmOpValueAsr1";
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let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
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}
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// A parameterized register class alternative to i32imm/i64imm from Target.td.
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def ixlenimm : Operand<XLenVT>;
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// Standalone (codegen-only) immleaf patterns.
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def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
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// Addressing modes.
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// Necessary because a frameindex can't be matched directly in a pattern.
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def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
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// Extract least significant 12 bits from an immediate value and sign extend
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// them.
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def LO12Sext : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),
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SDLoc(N), N->getValueType(0));
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}]>;
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// Extract the most significant 20 bits from an immediate value. Add 1 if bit
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// 11 is 1, to compensate for the low 12 bits in the matching immediate addi
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// or ld/st being negative.
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def HI20 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
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SDLoc(N), N->getValueType(0));
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class BranchCC_rri<bits<3> funct3, string opcodestr>
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: RVInstB<funct3, OPC_BRANCH, (outs),
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(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
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opcodestr, "$rs1, $rs2, $imm12"> {
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let isBranch = 1;
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let isTerminator = 1;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class Load_ri<bits<3> funct3, string opcodestr>
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: RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
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opcodestr, "$rd, ${imm12}(${rs1})">;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class Store_rri<bits<3> funct3, string opcodestr>
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: RVInstS<funct3, OPC_STORE, (outs),
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(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
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opcodestr, "$rs2, ${imm12}(${rs1})">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class ALU_ri<bits<3> funct3, string opcodestr>
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: RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
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opcodestr, "$rd, $rs1, $imm12">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr>
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: RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
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(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
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"$rd, $rs1, $shamt">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class CSR_ir<bits<3> funct3, string opcodestr>
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: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins uimm12:$imm12, GPR:$rs1),
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opcodestr, "$rd, $imm12, $rs1">;
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class CSR_ii<bits<3> funct3, string opcodestr>
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: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
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(ins uimm12:$imm12, uimm5:$rs1),
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opcodestr, "$rd, $imm12, $rs1">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr>
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: RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
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(ins GPR:$rs1, uimm5:$shamt), opcodestr,
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"$rd, $rs1, $shamt">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class Priv<string opcodestr, bits<7> funct7>
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: RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
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opcodestr, "">;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20:$imm20),
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"lui", "$rd, $imm20">;
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def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20:$imm20),
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"auipc", "$rd, $imm20">;
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let isCall = 1 in
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def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0:$imm20),
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"jal", "$rd, $imm20">;
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let isCall = 1 in
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def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
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(ins GPR:$rs1, simm12:$imm12),
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"jalr", "$rd, $rs1, $imm12">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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def BEQ : BranchCC_rri<0b000, "beq">;
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def BNE : BranchCC_rri<0b001, "bne">;
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def BLT : BranchCC_rri<0b100, "blt">;
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def BGE : BranchCC_rri<0b101, "bge">;
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def BLTU : BranchCC_rri<0b110, "bltu">;
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def BGEU : BranchCC_rri<0b111, "bgeu">;
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def LB : Load_ri<0b000, "lb">;
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def LH : Load_ri<0b001, "lh">;
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def LW : Load_ri<0b010, "lw">;
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def LBU : Load_ri<0b100, "lbu">;
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def LHU : Load_ri<0b101, "lhu">;
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def SB : Store_rri<0b000, "sb">;
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def SH : Store_rri<0b001, "sh">;
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def SW : Store_rri<0b010, "sw">;
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def ADDI : ALU_ri<0b000, "addi">;
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def SLTI : ALU_ri<0b010, "slti">;
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def SLTIU : ALU_ri<0b011, "sltiu">;
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def XORI : ALU_ri<0b100, "xori">;
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def ORI : ALU_ri<0b110, "ori">;
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def ANDI : ALU_ri<0b111, "andi">;
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def SLLI : Shift_ri<0, 0b001, "slli">;
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def SRLI : Shift_ri<0, 0b101, "srli">;
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def SRAI : Shift_ri<1, 0b101, "srai">;
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def ADD : ALU_rr<0b0000000, 0b000, "add">;
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def SUB : ALU_rr<0b0100000, 0b000, "sub">;
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def SLL : ALU_rr<0b0000000, 0b001, "sll">;
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def SLT : ALU_rr<0b0000000, 0b010, "slt">;
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def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
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def XOR : ALU_rr<0b0000000, 0b100, "xor">;
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def SRL : ALU_rr<0b0000000, 0b101, "srl">;
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def SRA : ALU_rr<0b0100000, 0b101, "sra">;
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def OR : ALU_rr<0b0000000, 0b110, "or">;
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def AND : ALU_rr<0b0000000, 0b111, "and">;
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
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def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
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(ins fencearg:$pred, fencearg:$succ),
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"fence", "$pred, $succ"> {
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bits<4> pred;
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bits<4> succ;
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let rs1 = 0;
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let rd = 0;
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let imm12 = {0b0000,pred,succ};
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}
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def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", ""> {
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let rs1 = 0;
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let rd = 0;
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let imm12 = 0;
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}
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def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", ""> {
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let rs1 = 0;
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let rd = 0;
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let imm12 = 0;
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}
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def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
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let rs1 = 0;
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let rd = 0;
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let imm12 = 1;
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}
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} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
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def CSRRW : CSR_ir<0b001, "csrrw">;
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def CSRRS : CSR_ir<0b010, "csrrs">;
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def CSRRC : CSR_ir<0b011, "csrrc">;
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def CSRRWI : CSR_ii<0b101, "csrrwi">;
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def CSRRSI : CSR_ii<0b110, "csrrsi">;
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def CSRRCI : CSR_ii<0b111, "csrrci">;
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/// RV64I instructions
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let Predicates = [IsRV64] in {
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def LWU : Load_ri<0b110, "lwu">;
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def LD : Load_ri<0b011, "ld">;
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def SD : Store_rri<0b011, "sd">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
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(ins GPR:$rs1, simm12:$imm12),
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"addiw", "$rd, $rs1, $imm12">;
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def SLLIW : ShiftW_ri<0, 0b001, "slliw">;
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def SRLIW : ShiftW_ri<0, 0b101, "srliw">;
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def SRAIW : ShiftW_ri<1, 0b101, "sraiw">;
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def ADDW : ALUW_rr<0b0000000, 0b000, "addw">;
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def SUBW : ALUW_rr<0b0100000, 0b000, "subw">;
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def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">;
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def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">;
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def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">;
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} // Predicates = [IsRV64]
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//===----------------------------------------------------------------------===//
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// Privileged instructions
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//===----------------------------------------------------------------------===//
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let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
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def URET : Priv<"uret", 0b0000000> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00010;
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}
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def SRET : Priv<"sret", 0b0001000> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00010;
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}
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def MRET : Priv<"mret", 0b0011000> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00010;
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}
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} // isBarrier = 1, isReturn = 1, isTerminator = 1
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def WFI : Priv<"wfi", 0b0001000> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00101;
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}
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
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(ins GPR:$rs1, GPR:$rs2),
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"sfence.vma", "$rs1, $rs2"> {
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let rd = 0;
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}
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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// TODO la
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// TODO lb lh lw
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// TODO RV64I: ld
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// TODO sb sh sw
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// TODO RV64I: sd
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def : InstAlias<"nop", (ADDI X0, X0, 0)>;
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// TODO li
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def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
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def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
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def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
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let Predicates = [IsRV64] in {
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def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
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def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>;
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} // Predicates = [IsRV64]
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def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>;
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def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
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def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
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def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
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def : InstAlias<"beqz $rs, $offset",
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(BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
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def : InstAlias<"bnez $rs, $offset",
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(BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
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def : InstAlias<"blez $rs, $offset",
|
|
(BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
|
|
def : InstAlias<"bgez $rs, $offset",
|
|
(BGE GPR:$rs, X0, simm13_lsb0:$offset)>;
|
|
def : InstAlias<"bltz $rs, $offset",
|
|
(BLT GPR:$rs, X0, simm13_lsb0:$offset)>;
|
|
def : InstAlias<"bgtz $rs, $offset",
|
|
(BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
|
|
|
|
// Always output the canonical mnemonic for the pseudo branch instructions.
|
|
// The GNU tools emit the canonical mnemonic for the branch pseudo instructions
|
|
// as well (e.g. "bgt" will be recognised by the assembler but never printed by
|
|
// objdump). Match this behaviour by setting a zero weight.
|
|
def : InstAlias<"bgt $rs, $rt, $offset",
|
|
(BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
|
|
def : InstAlias<"ble $rs, $rt, $offset",
|
|
(BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
|
|
def : InstAlias<"bgtu $rs, $rt, $offset",
|
|
(BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
|
|
def : InstAlias<"bleu $rs, $rt, $offset",
|
|
(BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
|
|
|
|
// "ret" has more weight since "ret" and "jr" alias the same "jalr" instruction.
|
|
def : InstAlias<"j $offset", (JAL X0, simm21_lsb0:$offset)>;
|
|
def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0:$offset)>;
|
|
def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0)>;
|
|
def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0)>;
|
|
def : InstAlias<"ret", (JALR X0, X1, 0), 2>;
|
|
// TODO call
|
|
// TODO tail
|
|
|
|
def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
|
|
|
|
// CSR Addresses: 0xC00 == cycle, 0xC01 == time, 0xC02 == instret
|
|
// 0xC80 == cycleh, 0xC81 == timeh, 0xC82 == instreth
|
|
def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, 0xC02, X0)>;
|
|
def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, 0xC00, X0)>;
|
|
def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, 0xC01, X0)>;
|
|
|
|
let Predicates = [IsRV32] in {
|
|
def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, 0xC82, X0)>;
|
|
def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, 0xC80, X0)>;
|
|
def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, 0xC81, X0)>;
|
|
} // Predicates = [IsRV32]
|
|
|
|
def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, uimm12:$csr, X0)>;
|
|
def : InstAlias<"csrw $csr, $rs", (CSRRW X0, uimm12:$csr, GPR:$rs)>;
|
|
def : InstAlias<"csrs $csr, $rs", (CSRRS X0, uimm12:$csr, GPR:$rs)>;
|
|
def : InstAlias<"csrc $csr, $rs", (CSRRC X0, uimm12:$csr, GPR:$rs)>;
|
|
|
|
def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
|
|
def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
|
|
def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
|
|
|
|
def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>;
|
|
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo-instructions and codegen patterns
|
|
//
|
|
// Naming convention: For 'generic' pattern classes, we use the naming
|
|
// convention PatTy1Ty2. For pattern classes which offer a more complex
|
|
// expension, prefix the class name, e.g. BccPat.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Generic pattern classes
|
|
|
|
class PatGprGpr<SDPatternOperator OpNode, RVInstR Inst>
|
|
: Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
|
|
class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>
|
|
: Pat<(OpNode GPR:$rs1, simm12:$imm12), (Inst GPR:$rs1, simm12:$imm12)>;
|
|
class PatGprUimmLog2XLen<SDPatternOperator OpNode, RVInstIShift Inst>
|
|
: Pat<(OpNode GPR:$rs1, uimmlog2xlen:$shamt),
|
|
(Inst GPR:$rs1, uimmlog2xlen:$shamt)>;
|
|
|
|
/// Predicates
|
|
|
|
def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
|
|
return isOrEquivalentToAdd(N);
|
|
}]>;
|
|
|
|
/// Immediates
|
|
|
|
def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
|
|
// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits.
|
|
def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
|
|
|
|
/// Simple arithmetic operations
|
|
|
|
def : PatGprGpr<add, ADD>;
|
|
def : PatGprSimm12<add, ADDI>;
|
|
def : PatGprGpr<sub, SUB>;
|
|
def : PatGprGpr<or, OR>;
|
|
def : PatGprSimm12<or, ORI>;
|
|
def : PatGprGpr<and, AND>;
|
|
def : PatGprSimm12<and, ANDI>;
|
|
def : PatGprGpr<xor, XOR>;
|
|
def : PatGprSimm12<xor, XORI>;
|
|
def : PatGprGpr<shl, SLL>;
|
|
def : PatGprUimmLog2XLen<shl, SLLI>;
|
|
def : PatGprGpr<srl, SRL>;
|
|
def : PatGprUimmLog2XLen<srl, SRLI>;
|
|
def : PatGprGpr<sra, SRA>;
|
|
def : PatGprUimmLog2XLen<sra, SRAI>;
|
|
|
|
/// FrameIndex calculations
|
|
|
|
def : Pat<(add (i32 AddrFI:$Rs), simm12:$imm12),
|
|
(ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
|
|
def : Pat<(IsOrAdd (i32 AddrFI:$Rs), simm12:$imm12),
|
|
(ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
|
|
|
|
/// Setcc
|
|
|
|
def : PatGprGpr<setlt, SLT>;
|
|
def : PatGprSimm12<setlt, SLTI>;
|
|
def : PatGprGpr<setult, SLTU>;
|
|
def : PatGprSimm12<setult, SLTIU>;
|
|
|
|
// Define pattern expansions for setcc operations that aren't directly
|
|
// handled by a RISC-V instruction.
|
|
def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
|
|
def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
|
|
def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
|
|
def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
|
|
def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
|
|
def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
|
|
def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
|
|
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
|
|
|
|
let usesCustomInserter = 1 in
|
|
def Select_GPR_Using_CC_GPR
|
|
: Pseudo<(outs GPR:$dst),
|
|
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$imm, GPR:$src, GPR:$src2),
|
|
[(set XLenVT:$dst, (SelectCC GPR:$lhs, GPR:$rhs,
|
|
(XLenVT imm:$imm), GPR:$src, GPR:$src2))]>;
|
|
|
|
/// Branches and jumps
|
|
|
|
// Match `(brcond (CondOp ..), ..)` and lower to the appropriate RISC-V branch
|
|
// instruction.
|
|
class BccPat<PatFrag CondOp, RVInstB Inst>
|
|
: Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
|
|
(Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
|
|
|
|
def : BccPat<seteq, BEQ>;
|
|
def : BccPat<setne, BNE>;
|
|
def : BccPat<setlt, BLT>;
|
|
def : BccPat<setge, BGE>;
|
|
def : BccPat<setult, BLTU>;
|
|
def : BccPat<setuge, BGEU>;
|
|
|
|
class BccSwapPat<PatFrag CondOp, RVInst InstBcc>
|
|
: Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
|
|
(InstBcc GPR:$rs2, GPR:$rs1, bb:$imm12)>;
|
|
|
|
// Condition codes that don't have matching RISC-V branch instructions, but
|
|
// are trivially supported by swapping the two input operands
|
|
def : BccSwapPat<setgt, BLT>;
|
|
def : BccSwapPat<setle, BGE>;
|
|
def : BccSwapPat<setugt, BLTU>;
|
|
def : BccSwapPat<setule, BGEU>;
|
|
|
|
// An extra pattern is needed for a brcond without a setcc (i.e. where the
|
|
// condition was calculated elsewhere).
|
|
def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
|
|
|
|
let isBarrier = 1, isBranch = 1, isTerminator = 1 in
|
|
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0:$imm20), [(br bb:$imm20)]>,
|
|
PseudoInstExpansion<(JAL X0, simm21_lsb0:$imm20)>;
|
|
|
|
let isCall = 1, Defs=[X1] in
|
|
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
|
|
def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>,
|
|
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
|
|
|
|
def : Pat<(brind GPR:$rs1), (PseudoBRIND GPR:$rs1, 0)>;
|
|
def : Pat<(brind (add GPR:$rs1, simm12:$imm12)),
|
|
(PseudoBRIND GPR:$rs1, simm12:$imm12)>;
|
|
|
|
let isCall = 1, Defs = [X1] in
|
|
def PseudoCALL : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
|
|
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
|
|
|
|
let isBarrier = 1, isReturn = 1, isTerminator = 1 in
|
|
def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
|
|
PseudoInstExpansion<(JALR X0, X1, 0)>;
|
|
|
|
/// Loads
|
|
|
|
multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
|
|
def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
|
|
def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>;
|
|
def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
|
|
(Inst GPR:$rs1, simm12:$imm12)>;
|
|
def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)),
|
|
(Inst AddrFI:$rs1, simm12:$imm12)>;
|
|
def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
|
|
(Inst AddrFI:$rs1, simm12:$imm12)>;
|
|
}
|
|
|
|
defm : LdPat<sextloadi8, LB>;
|
|
defm : LdPat<extloadi8, LB>;
|
|
defm : LdPat<sextloadi16, LH>;
|
|
defm : LdPat<extloadi16, LH>;
|
|
defm : LdPat<load, LW>;
|
|
defm : LdPat<zextloadi8, LBU>;
|
|
defm : LdPat<zextloadi16, LHU>;
|
|
|
|
/// Stores
|
|
|
|
multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
|
|
def : Pat<(StoreOp StTy:$rs2, GPR:$rs1), (Inst StTy:$rs2, GPR:$rs1, 0)>;
|
|
def : Pat<(StoreOp StTy:$rs2, AddrFI:$rs1), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
|
|
def : Pat<(StoreOp StTy:$rs2, (add GPR:$rs1, simm12:$imm12)),
|
|
(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
|
|
def : Pat<(StoreOp StTy:$rs2, (add AddrFI:$rs1, simm12:$imm12)),
|
|
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
|
|
def : Pat<(StoreOp StTy:$rs2, (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
|
|
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
|
|
}
|
|
|
|
defm : StPat<truncstorei8, SB, GPR>;
|
|
defm : StPat<truncstorei16, SH, GPR>;
|
|
defm : StPat<store, SW, GPR>;
|
|
|
|
/// Other pseudo-instructions
|
|
|
|
// Pessimistically assume the stack pointer will be clobbered
|
|
let Defs = [X2], Uses = [X2] in {
|
|
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|
[(CallSeqStart timm:$amt1, timm:$amt2)]>;
|
|
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|
[(CallSeqEnd timm:$amt1, timm:$amt2)]>;
|
|
} // Defs = [X2], Uses = [X2]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Standard extensions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "RISCVInstrInfoM.td"
|
|
include "RISCVInstrInfoA.td"
|
|
include "RISCVInstrInfoF.td"
|
|
include "RISCVInstrInfoD.td"
|
|
include "RISCVInstrInfoC.td"
|