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llvm-project/llvm/lib/Target/Hexagon
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Eric Astor 8d5bf0422b [ms] [llvm-ml] Add support for attempted register parsing 
Summary:
Add a new method (tryParseRegister) that attempts to parse a register specification.

MASM allows the use of IFDEF <register>, as well as IFDEF <symbol>. To accommodate this, we make it possible to check whether a register specification can be parsed at the current location, without failing the entire parse if it can't.

Reviewers: thakis

Reviewed By: thakis

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73486
 		2020-02-11 10:45:33 -05:00
..
AsmParser [ms] [llvm-ml] Add support for attempted register parsing 2020-02-11 10:45:33 -05:00
Disassembler [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
MCTargetDesc Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
BitTracker.cpp [Hexagon] Fixes -Wrange-loop-analysis warnings 2019-12-22 19:35:02 +01:00
BitTracker.h
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CMakeLists.txt
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Hexagon.h
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Hexagon.td [Hexagon] Rename FeatureHasPreV65 to FeaturePreV65 2020-02-03 08:20:59 -06:00
HexagonArch.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonAsmPrinter.cpp CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
HexagonAsmPrinter.h Include what you use in HexagonAsmPrinter.h 2019-06-03 11:41:18 +00:00
HexagonBitSimplify.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonBitTracker.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonBitTracker.h
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HexagonBlockRanges.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
HexagonBlockRanges.h
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HexagonBranchRelaxation.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonCFGOptimizer.cpp
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HexagonCallingConv.td
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HexagonCommonGEP.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonConstExtenders.cpp [Hexagon] Add a target feature to disable compound instructions 2020-01-16 12:37:30 -06:00
HexagonConstPropagation.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonCopyToCombine.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepDecoders.inc [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepIICHVX.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepIICScalar.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepITypes.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepITypes.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepInstrFormats.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepInstrInfo.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMapAsm2Intrin.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMappings.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMask.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepOperands.td [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepTimingClasses.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonEarlyIfConv.cpp Fix "pointer is null" static analyzer warnings. NFCI. 2020-01-10 11:10:42 +00:00
HexagonExpandCondsets.cpp Make more use of MachineInstr::mayLoadOrStore. 2019-12-19 11:51:52 +00:00
HexagonFixupHwLoops.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonFrameLowering.cpp ArrayRef'ize spillCalleeSavedRegisters. NFCI. 2020-02-08 12:19:23 +01:00
HexagonFrameLowering.h ArrayRef'ize spillCalleeSavedRegisters. NFCI. 2020-02-08 12:19:23 +01:00
HexagonGenExtract.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonGenInsert.cpp Reland 'Fixed -Wdeprecated-copy warnings. NFCI.' 2019-11-23 23:09:39 +01:00
HexagonGenMux.cpp [Hexagon] Validate the iterators before converting them to mux. 2019-11-14 13:01:16 -06:00
HexagonGenPredicate.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonHardwareLoops.cpp Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
HexagonHazardRecognizer.cpp
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HexagonHazardRecognizer.h
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HexagonIICHVX.td
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HexagonIICScalar.td
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HexagonISelDAGToDAG.cpp [Hexagon] Add a target feature to disable compound instructions 2020-01-16 12:37:30 -06:00
HexagonISelDAGToDAG.h [Hexagon] Update PS_aligna with max stack alignment once isel completes 2019-11-12 11:47:29 -06:00
HexagonISelDAGToDAGHVX.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonISelLowering.cpp [NFC] Introduce an API for MemOp 2020-02-07 11:32:27 +01:00
HexagonISelLowering.h [NFC] Introduce a type to model memory operation 2020-01-31 17:29:01 +01:00
HexagonISelLoweringHVX.cpp [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal' 2020-01-03 03:26:41 +00:00
HexagonInstrFormats.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonInstrFormatsV60.td
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HexagonInstrFormatsV65.td
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HexagonInstrInfo.cpp [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
HexagonInstrInfo.h [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
HexagonIntrinsics.td [Hexagon] Remove incorrect intrinsic definition and invalid testcase 2019-11-21 09:18:15 -06:00
HexagonIntrinsicsV5.td
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HexagonIntrinsicsV60.td
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HexagonLoopIdiomRecognition.cpp Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC)." 2020-01-04 18:44:38 +00:00
HexagonMCInstLower.cpp
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HexagonMachineFunctionInfo.cpp
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HexagonMachineFunctionInfo.h Add support for Linux/Musl ABI 2020-01-20 09:59:56 -06:00
HexagonMachineScheduler.cpp
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HexagonMachineScheduler.h
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HexagonMapAsm2IntrinV62.gen.td
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HexagonMapAsm2IntrinV65.gen.td
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HexagonNewValueJump.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonOperands.td
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HexagonOptAddrMode.cpp HexagonOptAddrMode::changeStore - fix null dereference warning (PR43463) 2020-02-03 16:50:04 +00:00
HexagonOptimizeSZextends.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonPatterns.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonPatternsHVX.td [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX 2019-09-23 14:33:27 +00:00
HexagonPatternsV65.td
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HexagonPeephole.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonPseudo.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonRDFOpt.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonRegisterInfo.cpp [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
HexagonRegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
HexagonRegisterInfo.td [NFC] Fix trivial typos in comments 2020-01-06 10:50:26 +00:00
HexagonSchedule.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonScheduleV5.td
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HexagonScheduleV55.td
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HexagonScheduleV60.td
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HexagonScheduleV62.td
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HexagonScheduleV65.td
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HexagonScheduleV66.td
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HexagonScheduleV67.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonScheduleV67T.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonSelectionDAGInfo.cpp
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HexagonSelectionDAGInfo.h
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HexagonSplitConst32AndConst64.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonSplitDouble.cpp Make more use of MachineInstr::mayLoadOrStore. 2019-12-19 11:51:52 +00:00
HexagonStoreWidening.cpp Make more use of MachineInstr::mayLoadOrStore. 2019-12-19 11:51:52 +00:00
HexagonSubtarget.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
HexagonSubtarget.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonTargetMachine.cpp [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonTargetMachine.h
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HexagonTargetObjectFile.cpp Revert "Honor -fuse-init-array when os is not specified on x86" 2019-12-17 07:36:59 -08:00
HexagonTargetObjectFile.h
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HexagonTargetStreamer.h
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HexagonTargetTransformInfo.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonTargetTransformInfo.h [ARM] Teach the Arm cost model that a Shift can be folded into other instructions 2019-12-09 10:24:33 +00:00
HexagonVExtract.cpp [Hexagon] Handle stack realignment in hexagon-vextract 2019-11-12 09:43:21 -06:00
HexagonVLIWPacketizer.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonVLIWPacketizer.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonVectorLoopCarriedReuse.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
HexagonVectorPrint.cpp
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LLVMBuild.txt
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RDFCopy.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
RDFCopy.h
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RDFDeadCode.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
RDFDeadCode.h
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RDFGraph.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RDFGraph.h
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RDFLiveness.cpp [Hexagon] Fixes -Wrange-loop-analysis warnings 2019-12-22 19:35:02 +01:00
RDFLiveness.h
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RDFRegisters.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
RDFRegisters.h Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00