forked from OSchip/llvm-project
afcff2d0d9
This fixes 2 problems in subregister hierarchies with multiple levels and tuples: 1) For bigger tuples computing secondary subregs would miss 2nd order effects. In the test case a register like `S10_S11_S12_S13_S14` with D5 = S10_S11, D6 = S12_S13 we would correctly compute sub0 = D5, sub1 = D6 but would miss the fact that we could now form ssub0_ssub1_ssub2_ssub3 (aka sub0_sub1) = D5_D6. This is fixed by changing computeSecondarySubRegs() to compute a fixpoint. 2) Fixing 1) exposed a problem where TableGen would create multiple names for effectively the same subregister index. In the test case the subregister index sub0 is composed from ssub0 and ssub1, and sub1 is composed from ssub2 and ssub3. TableGen should not create both sub0_sub1 and ssub0_ssub1_ssub2_ssub3 as infered subregister indexes. This changes the code to build a transitive closure of the subregister components before forming new concatenated subregister indexes. This fix was developed for an out of tree target. For the in-tree targets the only change is in the register information computed for ARM. There is a slight chance this fixed/improved some register coalescing around the QQQQ/QQ register classes there but I couldn't see/provoke any code generation differences. Differential Revision: https://reviews.llvm.org/D36913 llvm-svn: 311914 |
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| .. | ||
| 2003-08-03-PassCode.td | ||
| 2006-09-18-LargeInt.td | ||
| 2010-03-24-PrematureDefaults.td | ||
| AnonDefinitionOnDemand.td | ||
| AsmPredicateCondsEmission.td | ||
| AsmVariant.td | ||
| BitOffsetDecoder.td | ||
| BitsInit.td | ||
| BitsInitOverflow.td | ||
| CStyleComment.td | ||
| ClassInstanceValue.td | ||
| ConcatenatedSubregs.td | ||
| Dag.td | ||
| DefmInherit.td | ||
| DefmInsideMultiClass.td | ||
| DuplicateFieldValues.td | ||
| FieldAccess.td | ||
| ForeachList.td | ||
| ForeachLoop.td | ||
| ForwardRef.td | ||
| GeneralList.td | ||
| GlobalISelEmitter.td | ||
| Include.inc | ||
| Include.td | ||
| IntBitInit.td | ||
| LazyChange.td | ||
| LetInsideMultiClasses.td | ||
| ListArgs.td | ||
| ListArgsSimple.td | ||
| ListConversion.td | ||
| ListManip.td | ||
| ListOfList.td | ||
| ListSlices.td | ||
| LoLoL.td | ||
| MultiClass.td | ||
| MultiClassDefName.td | ||
| MultiClassInherit.td | ||
| MultiPat.td | ||
| NestedForeach.td | ||
| Paste.td | ||
| RegisterBankEmitter.td | ||
| RegisterEncoder.td | ||
| SetTheory.td | ||
| SiblingForeach.td | ||
| Slice.td | ||
| String.td | ||
| SuperSubclassSameName.td | ||
| TargetInstrInfo.td | ||
| TargetInstrSpec.td | ||
| TemplateArgRename.td | ||
| Tree.td | ||
| TreeNames.td | ||
| TwoLevelName.td | ||
| UnsetBitInit.td | ||
| UnterminatedComment.td | ||
| ValidIdentifiers.td | ||
| cast-list-initializer.td | ||
| cast.td | ||
| defmclass.td | ||
| eq.td | ||
| eqbit.td | ||
| foreach.td | ||
| if-empty-list-arg.td | ||
| if.td | ||
| ifbit.td | ||
| intrinsic-long-name.td | ||
| intrinsic-varargs.td | ||
| lisp.td | ||
| list-element-bitref.td | ||
| listconcat.td | ||
| lit.local.cfg | ||
| math.td | ||
| nested-comment.td | ||
| pr8330.td | ||
| strconcat.td | ||
| subst.td | ||
| subst2.td | ||
| trydecode-emission.td | ||
| trydecode-emission2.td | ||
| trydecode-emission3.td | ||
| usevalname.td | ||