forked from OSchip/llvm-project
e6ae6767d9
The way the named arguments for various system instructions are handled at the
moment has a few problems:
- Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
- That weird Mapping class that I have no idea what I was on when I thought
it was a good idea.
- Searches are performed linearly through the entire list.
- We print absolutely all registers in upper-case, even though some are
canonically mixed case (SPSel for example).
- The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
to comments in our implementation, with a slightly opaque hex value
indicating the canonical encoding LLVM will use.
This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.
llvm-svn: 274576
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| .. | ||
| a64-ignored-fields.txt | ||
| arm64-advsimd.txt | ||
| arm64-arithmetic.txt | ||
| arm64-basic-a64-undefined.txt | ||
| arm64-bitfield.txt | ||
| arm64-branch.txt | ||
| arm64-canonical-form.txt | ||
| arm64-crc32.txt | ||
| arm64-crypto.txt | ||
| arm64-invalid-logical.txt | ||
| arm64-logical.txt | ||
| arm64-memory.txt | ||
| arm64-non-apple-fmov.txt | ||
| arm64-scalar-fp.txt | ||
| arm64-system.txt | ||
| armv8.1a-atomic.txt | ||
| armv8.1a-lor.txt | ||
| armv8.1a-pan.txt | ||
| armv8.1a-rdma.txt | ||
| armv8.1a-vhe.txt | ||
| armv8.2a-at.txt | ||
| armv8.2a-mmfr2.txt | ||
| armv8.2a-persistent-memory.txt | ||
| armv8.2a-statistical-profiling.txt | ||
| armv8.2a-uao.txt | ||
| basic-a64-instructions.txt | ||
| basic-a64-undefined.txt | ||
| basic-a64-unpredictable.txt | ||
| fullfp16-neg.txt | ||
| fullfp16-neon-neg.txt | ||
| gicv3-regs.txt | ||
| ldp-offset-predictable.txt | ||
| ldp-postind.predictable.txt | ||
| ldp-preind.predictable.txt | ||
| lit.local.cfg | ||
| neon-instructions.txt | ||
| ras-extension.txt | ||
| trace-regs.txt | ||