forked from OSchip/llvm-project
52 lines
1.7 KiB
C++
52 lines
1.7 KiB
C++
//===- X86LegalizerInfo.h ------------------------------------------*- C++
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//-*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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namespace llvm {
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class X86Subtarget;
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class X86TargetMachine;
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/// This class provides the information for the target register banks.
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class X86LegalizerInfo : public LegalizerInfo {
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private:
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/// Keep a reference to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget &Subtarget;
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const X86TargetMachine &TM;
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public:
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X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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private:
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void setLegalizerInfo32bit();
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void setLegalizerInfo64bit();
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void setLegalizerInfoSSE1();
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void setLegalizerInfoSSE2();
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void setLegalizerInfoSSE41();
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void setLegalizerInfoAVX();
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void setLegalizerInfoAVX2();
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void setLegalizerInfoAVX512();
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void setLegalizerInfoAVX512DQ();
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void setLegalizerInfoAVX512BW();
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};
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} // namespace llvm
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#endif
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