forked from OSchip/llvm-project
485 lines
16 KiB
LLVM
485 lines
16 KiB
LLVM
; Test the MSA intrinsics that are encoded with the 3RF instruction format.
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fadd_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fadd_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fadd.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fadd_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fadd.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fadd_w_test
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;
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@llvm_mips_fadd_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fadd_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fadd_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fadd_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fadd.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fadd_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fadd.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fadd_d_test
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define void @fadd_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fadd_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fadd_w_ARG2
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%2 = fadd <4 x float> %0, %1
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store <4 x float> %2, <4 x float>* @llvm_mips_fadd_w_RES
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ret void
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}
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; CHECK: fadd_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fadd.w
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; CHECK: st.w
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; CHECK: .size fadd_w_test
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define void @fadd_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fadd_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fadd_d_ARG2
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%2 = fadd <2 x double> %0, %1
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store <2 x double> %2, <2 x double>* @llvm_mips_fadd_d_RES
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ret void
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}
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; CHECK: fadd_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fadd.d
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; CHECK: st.d
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; CHECK: .size fadd_d_test
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;
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@llvm_mips_fdiv_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fdiv_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fdiv_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fdiv_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fdiv.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fdiv_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fdiv.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fdiv_w_test
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;
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@llvm_mips_fdiv_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fdiv_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fdiv_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fdiv_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fdiv.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fdiv_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fdiv.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fdiv_d_test
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define void @fdiv_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fdiv_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fdiv_w_ARG2
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%2 = fdiv <4 x float> %0, %1
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store <4 x float> %2, <4 x float>* @llvm_mips_fdiv_w_RES
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ret void
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}
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; CHECK: fdiv_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fdiv.w
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; CHECK: st.w
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; CHECK: .size fdiv_w_test
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define void @fdiv_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fdiv_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fdiv_d_ARG2
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%2 = fdiv <2 x double> %0, %1
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store <2 x double> %2, <2 x double>* @llvm_mips_fdiv_d_RES
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ret void
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}
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; CHECK: fdiv_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fdiv.d
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; CHECK: st.d
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; CHECK: .size fdiv_d_test
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;
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@llvm_mips_fmin_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fmin_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fmin_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fmin_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fmin_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fmin_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fmin_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fmin_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fmin.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fmin_w_test
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;
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@llvm_mips_fmin_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fmin_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fmin_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fmin_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fmin_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fmin_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fmin_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fmin_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fmin.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fmin_d_test
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;
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@llvm_mips_fmin_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fmin_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fmin_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fmin_a_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fmin_a_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fmin_a_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fmin.a.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fmin_a_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fmin.a.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fmin_a_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fmin_a.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fmin_a_w_test
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;
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@llvm_mips_fmin_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fmin_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fmin_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fmin_a_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fmin_a_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fmin_a_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fmin.a.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fmin_a_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fmin.a.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fmin_a_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fmin_a.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fmin_a_d_test
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;
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@llvm_mips_fmax_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fmax_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fmax_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fmax_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fmax_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fmax_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fmax_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fmax_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fmax.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fmax_w_test
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;
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@llvm_mips_fmax_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fmax_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fmax_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fmax_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fmax_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fmax_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fmax_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fmax_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fmax.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fmax_d_test
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;
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@llvm_mips_fmax_a_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fmax_a_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fmax_a_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fmax_a_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fmax_a_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fmax_a_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fmax.a.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fmax_a_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fmax_a_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fmax_a.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fmax_a_w_test
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;
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@llvm_mips_fmax_a_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fmax_a_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
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@llvm_mips_fmax_a_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_fmax_a_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fmax_a_d_ARG1
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%1 = load <2 x double>* @llvm_mips_fmax_a_d_ARG2
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%2 = tail call <2 x double> @llvm.mips.fmax.a.d(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @llvm_mips_fmax_a_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>) nounwind
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; CHECK: llvm_mips_fmax_a_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: fmax_a.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_fmax_a_d_test
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;
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@llvm_mips_fmul_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fmul_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
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@llvm_mips_fmul_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_fmul_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
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%1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
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%2 = tail call <4 x float> @llvm.mips.fmul.w(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) nounwind
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; CHECK: llvm_mips_fmul_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: fmul.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_fmul_w_test
|
|
;
|
|
@llvm_mips_fmul_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
|
|
@llvm_mips_fmul_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
|
|
@llvm_mips_fmul_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_fmul_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
|
|
%1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
|
|
%2 = tail call <2 x double> @llvm.mips.fmul.d(<2 x double> %0, <2 x double> %1)
|
|
store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>) nounwind
|
|
|
|
; CHECK: llvm_mips_fmul_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: fmul.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_fmul_d_test
|
|
|
|
define void @fmul_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x float>* @llvm_mips_fmul_w_ARG1
|
|
%1 = load <4 x float>* @llvm_mips_fmul_w_ARG2
|
|
%2 = fmul <4 x float> %0, %1
|
|
store <4 x float> %2, <4 x float>* @llvm_mips_fmul_w_RES
|
|
ret void
|
|
}
|
|
|
|
; CHECK: fmul_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: fmul.w
|
|
; CHECK: st.w
|
|
; CHECK: .size fmul_w_test
|
|
|
|
define void @fmul_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x double>* @llvm_mips_fmul_d_ARG1
|
|
%1 = load <2 x double>* @llvm_mips_fmul_d_ARG2
|
|
%2 = fmul <2 x double> %0, %1
|
|
store <2 x double> %2, <2 x double>* @llvm_mips_fmul_d_RES
|
|
ret void
|
|
}
|
|
|
|
; CHECK: fmul_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: fmul.d
|
|
; CHECK: st.d
|
|
; CHECK: .size fmul_d_test
|
|
;
|
|
@llvm_mips_fsub_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
|
|
@llvm_mips_fsub_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
|
|
@llvm_mips_fsub_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_fsub_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
|
|
%1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
|
|
%2 = tail call <4 x float> @llvm.mips.fsub.w(<4 x float> %0, <4 x float> %1)
|
|
store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>) nounwind
|
|
|
|
; CHECK: llvm_mips_fsub_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: fsub.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_fsub_w_test
|
|
;
|
|
@llvm_mips_fsub_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
|
|
@llvm_mips_fsub_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
|
|
@llvm_mips_fsub_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_fsub_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
|
|
%1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
|
|
%2 = tail call <2 x double> @llvm.mips.fsub.d(<2 x double> %0, <2 x double> %1)
|
|
store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>) nounwind
|
|
|
|
; CHECK: llvm_mips_fsub_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: fsub.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_fsub_d_test
|
|
;
|
|
|
|
define void @fsub_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x float>* @llvm_mips_fsub_w_ARG1
|
|
%1 = load <4 x float>* @llvm_mips_fsub_w_ARG2
|
|
%2 = fsub <4 x float> %0, %1
|
|
store <4 x float> %2, <4 x float>* @llvm_mips_fsub_w_RES
|
|
ret void
|
|
}
|
|
|
|
; CHECK: fsub_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: fsub.w
|
|
; CHECK: st.w
|
|
; CHECK: .size fsub_w_test
|
|
|
|
define void @fsub_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x double>* @llvm_mips_fsub_d_ARG1
|
|
%1 = load <2 x double>* @llvm_mips_fsub_d_ARG2
|
|
%2 = fsub <2 x double> %0, %1
|
|
store <2 x double> %2, <2 x double>* @llvm_mips_fsub_d_RES
|
|
ret void
|
|
}
|
|
|
|
; CHECK: fsub_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: fsub.d
|
|
; CHECK: st.d
|
|
; CHECK: .size fsub_d_test
|