forked from OSchip/llvm-project
1196 lines
47 KiB
TableGen
1196 lines
47 KiB
TableGen
//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file contains the required infrastructure to support code generation
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/// for the standard 'V' (Vector) extension, version 0.9. This version is still
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/// experimental as the 'V' extension hasn't been ratified yet.
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///
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/// This file is included from RISCVInstrInfoV.td
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///
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//===----------------------------------------------------------------------===//
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// X0 has special meaning for vsetvl/vsetvli.
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// rd | rs1 | AVL value | Effect on vl
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//--------------------------------------------------------------
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// !X0 | X0 | VLMAX | Set vl to VLMAX
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// X0 | X0 | Value in vl | Keep current vl, just change vtype.
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def NoX0 : SDNodeXForm<undef,
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[{
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auto *C = dyn_cast<ConstantSDNode>(N);
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if (C && C->isNullValue()) {
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SDLoc DL(N);
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return SDValue(CurDAG->getMachineNode(RISCV::ADDI, DL, Subtarget->getXLenVT(),
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CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()),
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CurDAG->getTargetConstant(0, DL, Subtarget->getXLenVT())), 0);
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}
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return SDValue(N, 0);
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}]>;
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//===----------------------------------------------------------------------===//
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// Utilities.
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//===----------------------------------------------------------------------===//
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// This class describes information associated to the LMUL.
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class LMULInfo<int lmul, VReg regclass, VReg wregclass, string mx> {
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bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
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VReg vrclass = regclass;
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VReg wvrclass = wregclass;
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string MX = mx;
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}
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// Associate LMUL with tablegen records of register classes.
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def V_M1 : LMULInfo<0b000, VR, VRM2, "M1">;
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def V_M2 : LMULInfo<0b001, VRM2, VRM4, "M2">;
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def V_M4 : LMULInfo<0b010, VRM4, VRM8, "M4">;
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def V_M8 : LMULInfo<0b011, VRM8, NoVReg, "M8">;
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def V_MF8 : LMULInfo<0b101, VR, VR, "MF8">;
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def V_MF4 : LMULInfo<0b110, VR, VR, "MF4">;
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def V_MF2 : LMULInfo<0b111, VR, VR, "MF2">;
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// Used to iterate over all possible LMULs.
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def MxList {
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list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
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}
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class shift_amount<int num> {
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int val = !if(!eq(num, 1), 0, !add(1, shift_amount<!srl(num, 1)>.val));
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}
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// Output pattern for X0 used to represent VLMAX in the pseudo instructions.
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def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
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// List of EEW.
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defvar EEWList = [8, 16, 32, 64];
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// We only model FPR32 for V instructions in RISCVInstrInfoV.td.
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// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
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// to FPR32 for V instructions is enough.
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class ToFPR32<ValueType type, DAGOperand operand, string name> {
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dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
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(EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32),
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!eq(!cast<string>(operand), !cast<string>(FPR16)):
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(SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16),
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!eq(1, 1):
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!dag(type, [operand], [name]));
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}
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//===----------------------------------------------------------------------===//
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// Vector register and vector group type information.
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//===----------------------------------------------------------------------===//
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class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
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ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR>
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{
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ValueType Vector = Vec;
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ValueType Mask = Mas;
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int SEW = Sew;
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VReg RegClass = Reg;
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LMULInfo LMul = M;
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ValueType Scalar = Scal;
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RegisterClass ScalarRegClass = ScalarReg;
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}
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class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
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VReg Reg, LMULInfo M, ValueType Scal = XLenVT,
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RegisterClass ScalarReg = GPR>
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: VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg>
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{
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ValueType VectorM1 = VecM1;
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}
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defset list<VTypeInfo> AllVectors = {
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defset list<VTypeInfo> AllIntegerVectors = {
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def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, VR, V_MF8>;
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def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, VR, V_MF4>;
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def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, VR, V_MF2>;
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def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, VR, V_M1>;
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def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
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def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
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def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, VR, V_M1>;
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def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
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def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, VR, V_M1>;
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def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, VR, V_M1>;
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def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
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def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
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def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
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def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
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def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
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def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
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def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
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def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
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def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
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def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
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def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
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def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
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}
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defset list<VTypeInfo> AllFloatVectors = {
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defset list<VTypeInfo> NoGroupFloatVectors = {
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def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, VR, V_MF4, f16, FPR16>;
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def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, VR, V_MF2, f16, FPR16>;
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def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, VR, V_M1, f16, FPR16>;
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def VF32MF2: VTypeInfo<vfloat32mf2_t,vbool64_t, 32, VR, V_MF2, f32, FPR32>;
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def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, VR, V_M1, f32, FPR32>;
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def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>;
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}
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defset list<GroupVTypeInfo> GroupFloatVectors = {
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def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16,
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VRM2, V_M2, f16, FPR16>;
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def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16,
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VRM4, V_M4, f16, FPR16>;
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def VF16M8: GroupVTypeInfo<vfloat16m8_t, vfloat16m1_t, vbool2_t, 16,
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VRM8, V_M8, f16, FPR16>;
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def VF32M2: GroupVTypeInfo<vfloat32m2_t, vfloat32m1_t, vbool16_t, 32,
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VRM2, V_M2, f32, FPR32>;
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def VF32M4: GroupVTypeInfo<vfloat32m4_t, vfloat32m1_t, vbool8_t, 32,
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VRM4, V_M4, f32, FPR32>;
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def VF32M8: GroupVTypeInfo<vfloat32m8_t, vfloat32m1_t, vbool4_t, 32,
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VRM8, V_M8, f32, FPR32>;
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def VF64M2: GroupVTypeInfo<vfloat64m2_t, vfloat64m1_t, vbool32_t, 64,
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VRM2, V_M2, f64, FPR64>;
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def VF64M4: GroupVTypeInfo<vfloat64m4_t, vfloat64m1_t, vbool16_t, 64,
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VRM4, V_M4, f64, FPR64>;
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def VF64M8: GroupVTypeInfo<vfloat64m8_t, vfloat64m1_t, vbool8_t, 64,
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VRM8, V_M8, f64, FPR64>;
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}
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}
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}
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class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti>
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{
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VTypeInfo Vti = vti;
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VTypeInfo Wti = wti;
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}
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defset list<VTypeInfoToWide> AllWidenableIntVectors = {
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def : VTypeInfoToWide<VI8MF8, VI16MF4>;
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def : VTypeInfoToWide<VI8MF4, VI16MF2>;
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def : VTypeInfoToWide<VI8MF2, VI16M1>;
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def : VTypeInfoToWide<VI8M1, VI16M2>;
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def : VTypeInfoToWide<VI8M2, VI16M4>;
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def : VTypeInfoToWide<VI8M4, VI16M8>;
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def : VTypeInfoToWide<VI16MF4, VI32MF2>;
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def : VTypeInfoToWide<VI16MF2, VI32M1>;
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def : VTypeInfoToWide<VI16M1, VI32M2>;
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def : VTypeInfoToWide<VI16M2, VI32M4>;
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def : VTypeInfoToWide<VI16M4, VI32M8>;
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def : VTypeInfoToWide<VI32MF2, VI64M1>;
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def : VTypeInfoToWide<VI32M1, VI64M2>;
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def : VTypeInfoToWide<VI32M2, VI64M4>;
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def : VTypeInfoToWide<VI32M4, VI64M8>;
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}
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// This class holds the record of the RISCVVPseudoTable below.
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// This represents the information we need in codegen for each pseudo.
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// The definition should be consistent with `struct PseudoInfo` in
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// RISCVBaseInfo.h.
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class CONST8b<bits<8> val> {
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bits<8> V = val;
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}
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def InvalidIndex : CONST8b<0x80>;
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class RISCVVPseudo {
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Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
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Instruction BaseInstr;
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bits<8> VLIndex = InvalidIndex.V;
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bits<8> SEWIndex = InvalidIndex.V;
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bits<8> MergeOpIndex = InvalidIndex.V;
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bits<3> VLMul;
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bit HasDummyMask = 0;
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}
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// The actual table.
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def RISCVVPseudosTable : GenericTable {
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let FilterClass = "RISCVVPseudo";
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let CppTypeName = "PseudoInfo";
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let Fields = [ "Pseudo", "BaseInstr", "VLIndex", "SEWIndex", "MergeOpIndex",
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"VLMul", "HasDummyMask" ];
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let PrimaryKey = [ "Pseudo" ];
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let PrimaryKeyName = "getPseudoInfo";
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}
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def RISCVVIntrinsicsTable : GenericTable {
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let FilterClass = "RISCVVIntrinsic";
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let CppTypeName = "RISCVVIntrinsicInfo";
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let Fields = ["IntrinsicID", "ExtendOperand"];
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let PrimaryKey = ["IntrinsicID"];
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let PrimaryKeyName = "getRISCVVIntrinsicInfo";
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}
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//===----------------------------------------------------------------------===//
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// Helpers to define the different pseudo instructions.
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//===----------------------------------------------------------------------===//
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class PseudoToVInst<string PseudoInst> {
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string VInst = !subst("_M8", "",
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!subst("_M4", "",
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!subst("_M2", "",
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!subst("_M1", "",
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!subst("_MF2", "",
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!subst("_MF4", "",
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!subst("_MF8", "",
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!subst("_MASK", "",
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!subst("Pseudo", "", PseudoInst)))))))));
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}
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// The destination vector register group for a masked vector instruction cannot
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// overlap the source mask register (v0), unless the destination vector register
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// is being written with a mask value (e.g., comparisons) or the scalar result
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// of a reduction.
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class GetVRegNoV0<VReg VRegClass> {
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VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
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!eq(VRegClass, VRM2) : VRM2NoV0,
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!eq(VRegClass, VRM4) : VRM4NoV0,
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!eq(VRegClass, VRM8) : VRM8NoV0,
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!eq(1, 1) : VRegClass);
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}
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// Join strings in list using separator and ignoring empty elements
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class Join<list<string> strings, string separator> {
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string ret = !foldl(!head(strings), !tail(strings), a, b,
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!cond(
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!and(!empty(a), !empty(b)) : "",
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!empty(a) : b,
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!empty(b) : a,
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1 : a#separator#b));
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}
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class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
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Pseudo<outs, ins, []>, RISCVVPseudo {
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let BaseInstr = instr;
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let VLMul = m.value;
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}
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class VPseudoUSLoadNoMask<VReg RetClass>:
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Pseudo<(outs RetClass:$rd),
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(ins GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
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RISCVVPseudo {
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let mayLoad = 1;
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let mayStore = 0;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Uses = [VL, VTYPE];
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let VLIndex = 2;
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let SEWIndex = 3;
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let HasDummyMask = 1;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoUSLoadMask<VReg RetClass>:
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$merge,
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GPR:$rs1,
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VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
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RISCVVPseudo {
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let mayLoad = 1;
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let mayStore = 0;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Constraints = "$rd = $merge";
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let Uses = [VL, VTYPE];
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let VLIndex = 4;
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let SEWIndex = 5;
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let MergeOpIndex = 1;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoUSStoreNoMask<VReg StClass>:
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Pseudo<(outs),
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(ins StClass:$rd, GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 1;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Uses = [VL, VTYPE];
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let VLIndex = 2;
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let SEWIndex = 3;
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let HasDummyMask = 1;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoUSStoreMask<VReg StClass>:
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Pseudo<(outs),
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(ins StClass:$rd, GPR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 1;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Uses = [VL, VTYPE];
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let VLIndex = 3;
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let SEWIndex = 4;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoBinaryNoMask<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class,
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string Constraint> :
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Pseudo<(outs RetClass:$rd),
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(ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Constraints = Constraint;
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let Uses = [VL, VTYPE];
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let VLIndex = 3;
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let SEWIndex = 4;
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let HasDummyMask = 1;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoBinaryMask<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class,
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string Constraint> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$merge,
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Op1Class:$rs2, Op2Class:$rs1,
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VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let usesCustomInserter = 1;
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let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
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let Uses = [VL, VTYPE];
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let VLIndex = 5;
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let SEWIndex = 6;
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let MergeOpIndex = 1;
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let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
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}
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class VPseudoBinaryCarryIn<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class,
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LMULInfo MInfo,
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bit CarryIn,
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string Constraint> :
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Pseudo<(outs RetClass:$rd),
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!if(!eq(CarryIn, 1),
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(ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl,
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ixlenimm:$sew),
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(ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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|
let hasSideEffects = 0;
|
|
let usesCustomInserter = 1;
|
|
let Constraints = Constraint;
|
|
let Uses = [VL, VTYPE];
|
|
let VLIndex = !if(!eq(CarryIn, 1), 4, 3);
|
|
let SEWIndex = !if(!eq(CarryIn, 1), 5, 4);
|
|
let MergeOpIndex = InvalidIndex.V;
|
|
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
|
|
let VLMul = MInfo.value;
|
|
}
|
|
|
|
multiclass VPseudoUSLoad {
|
|
foreach lmul = MxList.m in {
|
|
defvar LInfo = lmul.MX;
|
|
defvar vreg = lmul.vrclass;
|
|
let VLMul = lmul.value in {
|
|
def "_V_" # LInfo : VPseudoUSLoadNoMask<vreg>;
|
|
def "_V_" # LInfo # "_MASK" : VPseudoUSLoadMask<vreg>;
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass VPseudoUSStore {
|
|
foreach lmul = MxList.m in {
|
|
defvar LInfo = lmul.MX;
|
|
defvar vreg = lmul.vrclass;
|
|
let VLMul = lmul.value in {
|
|
def "_V_" # LInfo : VPseudoUSStoreNoMask<vreg>;
|
|
def "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg>;
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass VPseudoBinary<VReg RetClass,
|
|
VReg Op1Class,
|
|
DAGOperand Op2Class,
|
|
LMULInfo MInfo,
|
|
string Constraint = ""> {
|
|
let VLMul = MInfo.value in {
|
|
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
|
|
Constraint>;
|
|
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class,
|
|
Constraint>;
|
|
}
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VV {
|
|
foreach m = MxList.m in
|
|
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VX<bit IsFloat> {
|
|
foreach m = MxList.m in
|
|
defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.vrclass, m.vrclass,
|
|
!if(!eq(IsFloat, 0), GPR, FPR32), m>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
|
|
foreach m = MxList.m in
|
|
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>;
|
|
}
|
|
|
|
// We use earlyclobber here due to
|
|
// * The destination EEW is smaller than the source EEW and the overlap is
|
|
// in the lowest-numbered part of the source register group is legal.
|
|
// Otherwise, it is illegal.
|
|
// * The destination EEW is greater than the source EEW, the source EMUL is
|
|
// at least 1, and the overlap is in the highest-numbered part of the
|
|
// destination register group is legal. Otherwise, it is illegal.
|
|
multiclass VPseudoBinaryW_VV {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryW_VX {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _VX : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryW_WV {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryW_WX {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _WX : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_WV {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_WX {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_WI {
|
|
foreach m = MxList.m[0-5] in
|
|
defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
|
|
"@earlyclobber $rd">;
|
|
}
|
|
|
|
// For vadc and vsbc, the instruction encoding is reserved if the destination
|
|
// vector register is v0.
|
|
// For vadc and vsbc, CarryIn == 1 and CarryOut == 0
|
|
multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
|
|
string Constraint = ""> {
|
|
foreach m = MxList.m in
|
|
def "_VV" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
|
|
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
|
|
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
|
|
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
|
|
m.vrclass, m.vrclass, m, CarryIn, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
|
|
string Constraint = ""> {
|
|
foreach m = MxList.m in
|
|
def "_VX" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
|
|
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
|
|
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
|
|
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
|
|
m.vrclass, GPR, m, CarryIn, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
|
|
string Constraint = ""> {
|
|
foreach m = MxList.m in
|
|
def "_VI" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
|
|
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
|
|
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
|
|
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
|
|
m.vrclass, simm5, m, CarryIn, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5> {
|
|
defm "" : VPseudoBinaryV_VV;
|
|
defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>;
|
|
defm "" : VPseudoBinaryV_VI<ImmType>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VV_VX<bit IsFloat = 0> {
|
|
defm "" : VPseudoBinaryV_VV;
|
|
defm "" : VPseudoBinaryV_VX<IsFloat>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> {
|
|
defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>;
|
|
defm "" : VPseudoBinaryV_VI<ImmType>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryW_VV_VX {
|
|
defm "" : VPseudoBinaryW_VV;
|
|
defm "" : VPseudoBinaryW_VX;
|
|
}
|
|
|
|
multiclass VPseudoBinaryW_WV_WX {
|
|
defm "" : VPseudoBinaryW_WV;
|
|
defm "" : VPseudoBinaryW_WX;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VM_XM_IM {
|
|
defm "" : VPseudoBinaryV_VM;
|
|
defm "" : VPseudoBinaryV_XM;
|
|
defm "" : VPseudoBinaryV_IM;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_VM_XM {
|
|
defm "" : VPseudoBinaryV_VM;
|
|
defm "" : VPseudoBinaryV_XM;
|
|
}
|
|
|
|
multiclass VPseudoBinaryM_VM_XM_IM<string Constraint> {
|
|
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>;
|
|
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>;
|
|
defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryM_VM_XM<string Constraint> {
|
|
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>;
|
|
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/1, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryM_V_X_I<string Constraint> {
|
|
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>;
|
|
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>;
|
|
defm "" : VPseudoBinaryV_IM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryM_V_X<string Constraint> {
|
|
defm "" : VPseudoBinaryV_VM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>;
|
|
defm "" : VPseudoBinaryV_XM</*CarryOut=*/1, /*CarryIn=*/0, Constraint>;
|
|
}
|
|
|
|
multiclass VPseudoBinaryV_WV_WX_WI {
|
|
defm "" : VPseudoBinaryV_WV;
|
|
defm "" : VPseudoBinaryV_WX;
|
|
defm "" : VPseudoBinaryV_WI;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Helpers to define the SDNode patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
multiclass VPatUSLoadStoreSDNode<LLVMType type,
|
|
LLVMType mask_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
RegisterClass reg_rs1,
|
|
VReg reg_class>
|
|
{
|
|
defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
|
|
defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
|
|
// Load
|
|
def : Pat<(type (load reg_rs1:$rs1)),
|
|
(load_instr reg_rs1:$rs1, VLMax, sew)>;
|
|
// Store
|
|
def : Pat<(store type:$rs2, reg_rs1:$rs1),
|
|
(store_instr reg_class:$rs2, reg_rs1:$rs1, VLMax, sew)>;
|
|
}
|
|
|
|
multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
|
|
foreach vti = AllVectors in
|
|
defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
|
|
reg_rs1, vti.RegClass>;
|
|
}
|
|
|
|
class VPatBinarySDNode<SDNode vop,
|
|
string instruction_name,
|
|
ValueType result_type,
|
|
ValueType op_type,
|
|
ValueType mask_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg RetClass,
|
|
VReg op_reg_class> :
|
|
Pat<(result_type (vop
|
|
(op_type op_reg_class:$rs1),
|
|
(op_type op_reg_class:$rs2))),
|
|
(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
|
|
op_reg_class:$rs1,
|
|
op_reg_class:$rs2,
|
|
VLMax, sew)>;
|
|
|
|
multiclass VPatBinarySDNode<SDNode vop, string instruction_name>
|
|
{
|
|
foreach vti = AllIntegerVectors in
|
|
def : VPatBinarySDNode<vop, instruction_name,
|
|
vti.Vector, vti.Vector, vti.Mask, vti.SEW,
|
|
vti.LMul, vti.RegClass, vti.RegClass>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Helpers to define the intrinsic patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
class VPatBinaryNoMask<string intrinsic_name,
|
|
string inst,
|
|
string kind,
|
|
ValueType result_type,
|
|
ValueType op1_type,
|
|
ValueType op2_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg op1_reg_class,
|
|
DAGOperand op2_kind> :
|
|
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
|
|
(op1_type op1_reg_class:$rs1),
|
|
(op2_type op2_kind:$rs2),
|
|
(XLenVT GPR:$vl))),
|
|
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
|
|
(op1_type op1_reg_class:$rs1),
|
|
ToFPR32<op2_type, op2_kind, "rs2">.ret,
|
|
(NoX0 GPR:$vl), sew)>;
|
|
|
|
class VPatBinaryMask<string intrinsic_name,
|
|
string inst,
|
|
string kind,
|
|
ValueType result_type,
|
|
ValueType op1_type,
|
|
ValueType op2_type,
|
|
ValueType mask_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg result_reg_class,
|
|
VReg op1_reg_class,
|
|
DAGOperand op2_kind> :
|
|
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
|
|
(result_type result_reg_class:$merge),
|
|
(op1_type op1_reg_class:$rs1),
|
|
(op2_type op2_kind:$rs2),
|
|
(mask_type V0),
|
|
(XLenVT GPR:$vl))),
|
|
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
|
|
(result_type result_reg_class:$merge),
|
|
(op1_type op1_reg_class:$rs1),
|
|
ToFPR32<op2_type, op2_kind, "rs2">.ret,
|
|
(mask_type V0), (NoX0 GPR:$vl), sew)>;
|
|
|
|
multiclass VPatBinary<string intrinsic,
|
|
string inst,
|
|
string kind,
|
|
ValueType result_type,
|
|
ValueType op1_type,
|
|
ValueType op2_type,
|
|
ValueType mask_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg result_reg_class,
|
|
VReg op1_reg_class,
|
|
DAGOperand op2_kind>
|
|
{
|
|
def : VPatBinaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
|
|
sew, vlmul, op1_reg_class, op2_kind>;
|
|
def : VPatBinaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
|
|
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
|
|
op2_kind>;
|
|
}
|
|
|
|
multiclass VPatBinaryCarryIn<string intrinsic,
|
|
string inst,
|
|
string kind,
|
|
ValueType result_type,
|
|
ValueType op1_type,
|
|
ValueType op2_type,
|
|
ValueType mask_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg op1_reg_class,
|
|
DAGOperand op2_kind>
|
|
{
|
|
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
|
|
(op1_type op1_reg_class:$rs1),
|
|
(op2_type op2_kind:$rs2),
|
|
(mask_type V0),
|
|
(XLenVT GPR:$vl))),
|
|
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
|
|
(op1_type op1_reg_class:$rs1),
|
|
ToFPR32<op2_type, op2_kind, "rs2">.ret,
|
|
(mask_type V0), (NoX0 GPR:$vl), sew)>;
|
|
}
|
|
|
|
multiclass VPatBinaryMaskOut<string intrinsic,
|
|
string inst,
|
|
string kind,
|
|
ValueType result_type,
|
|
ValueType op1_type,
|
|
ValueType op2_type,
|
|
int sew,
|
|
LMULInfo vlmul,
|
|
VReg op1_reg_class,
|
|
DAGOperand op2_kind>
|
|
{
|
|
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
|
|
(op1_type op1_reg_class:$rs1),
|
|
(op2_type op2_kind:$rs2),
|
|
(XLenVT GPR:$vl))),
|
|
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
|
|
(op1_type op1_reg_class:$rs1),
|
|
ToFPR32<op2_type, op2_kind, "rs2">.ret,
|
|
(NoX0 GPR:$vl), sew)>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VV<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist> {
|
|
foreach vti = vtilist in
|
|
defm : VPatBinary<intrinsic, instruction, "VV",
|
|
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
|
|
vti.SEW, vti.LMul, vti.RegClass,
|
|
vti.RegClass, vti.RegClass>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VX<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist> {
|
|
foreach vti = vtilist in
|
|
defm : VPatBinary<intrinsic, instruction,
|
|
!if(!eq(vti.Scalar, XLenVT), "VX", "VF"),
|
|
vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
|
|
vti.SEW, vti.LMul, vti.RegClass,
|
|
vti.RegClass, vti.ScalarRegClass>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VI<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist, Operand imm_type> {
|
|
foreach vti = vtilist in
|
|
defm : VPatBinary<intrinsic, instruction, "VI",
|
|
vti.Vector, vti.Vector, XLenVT, vti.Mask,
|
|
vti.SEW, vti.LMul, vti.RegClass,
|
|
vti.RegClass, imm_type>;
|
|
}
|
|
|
|
multiclass VPatBinaryW_VV<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "VV",
|
|
Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Wti.RegClass,
|
|
Vti.RegClass, Vti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryW_VX<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "VX",
|
|
Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Wti.RegClass,
|
|
Vti.RegClass, GPR>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryW_WV<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "WV",
|
|
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Wti.RegClass,
|
|
Wti.RegClass, Vti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryW_WX<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "WX",
|
|
Wti.Vector, Wti.Vector, XLenVT, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Wti.RegClass,
|
|
Wti.RegClass, GPR>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryV_WV<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "WV",
|
|
Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Vti.RegClass,
|
|
Wti.RegClass, Vti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryV_WX<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "WX",
|
|
Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Vti.RegClass,
|
|
Wti.RegClass, GPR>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryV_WI<string intrinsic, string instruction> {
|
|
foreach VtiToWti = AllWidenableIntVectors in {
|
|
defvar Vti = VtiToWti.Vti;
|
|
defvar Wti = VtiToWti.Wti;
|
|
defm : VPatBinary<intrinsic, instruction, "WI",
|
|
Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
|
|
Vti.SEW, Vti.LMul, Vti.RegClass,
|
|
Wti.RegClass, uimm5>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatBinaryV_VM<string intrinsic, string instruction,
|
|
bit CarryOut = 0> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
|
|
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
|
|
vti.Vector, vti.Vector, vti.Mask,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, vti.RegClass>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_XM<string intrinsic, string instruction,
|
|
bit CarryOut = 0> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryCarryIn<intrinsic, instruction, "VXM",
|
|
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
|
|
vti.Vector, XLenVT, vti.Mask,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, GPR>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_IM<string intrinsic, string instruction,
|
|
bit CarryOut = 0> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",
|
|
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
|
|
vti.Vector, XLenVT, vti.Mask,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, simm5>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_V<string intrinsic, string instruction> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryMaskOut<intrinsic, instruction, "VV",
|
|
vti.Mask, vti.Vector, vti.Vector,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, vti.RegClass>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_X<string intrinsic, string instruction> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryMaskOut<intrinsic, instruction, "VX",
|
|
vti.Mask, vti.Vector, XLenVT,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, GPR>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_I<string intrinsic, string instruction> {
|
|
foreach vti = AllIntegerVectors in
|
|
defm : VPatBinaryMaskOut<intrinsic, instruction, "VI",
|
|
vti.Mask, vti.Vector, XLenVT,
|
|
vti.SEW, vti.LMul,
|
|
vti.RegClass, simm5>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist, Operand ImmType = simm5>
|
|
{
|
|
defm "" : VPatBinaryV_VV<intrinsic, instruction, vtilist>;
|
|
defm "" : VPatBinaryV_VX<intrinsic, instruction, vtilist>;
|
|
defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist>
|
|
{
|
|
defm "" : VPatBinaryV_VV<intrinsic, instruction, vtilist>;
|
|
defm "" : VPatBinaryV_VX<intrinsic, instruction, vtilist>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
|
|
list<VTypeInfo> vtilist>
|
|
{
|
|
defm "" : VPatBinaryV_VX<intrinsic, instruction, vtilist>;
|
|
defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>;
|
|
}
|
|
|
|
multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryW_VV<intrinsic, instruction>;
|
|
defm "" : VPatBinaryW_VX<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryW_WV<intrinsic, instruction>;
|
|
defm "" : VPatBinaryW_WX<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_WV<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_WX<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_WI<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_VM<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_XM<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_IM<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryM_VM_XM_IM<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_VM<intrinsic, instruction, /*CarryOut=*/1>;
|
|
defm "" : VPatBinaryV_XM<intrinsic, instruction, /*CarryOut=*/1>;
|
|
defm "" : VPatBinaryV_IM<intrinsic, instruction, /*CarryOut=*/1>;
|
|
}
|
|
|
|
multiclass VPatBinaryM_V_X_I<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_V<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_X<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_I<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryV_VM_XM<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_VM<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_XM<intrinsic, instruction>;
|
|
}
|
|
|
|
multiclass VPatBinaryM_VM_XM<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_VM<intrinsic, instruction, /*CarryOut=*/1>;
|
|
defm "" : VPatBinaryV_XM<intrinsic, instruction, /*CarryOut=*/1>;
|
|
}
|
|
|
|
multiclass VPatBinaryM_V_X<string intrinsic, string instruction>
|
|
{
|
|
defm "" : VPatBinaryV_V<intrinsic, instruction>;
|
|
defm "" : VPatBinaryV_X<intrinsic, instruction>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions and patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Predicates = [HasStdExtV] in {
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo Instructions for CodeGen
|
|
//===----------------------------------------------------------------------===//
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
|
def PseudoVMV1R_V : VPseudo<VMV1R_V, V_M1, (outs VR:$vd), (ins VR:$vs2)>;
|
|
def PseudoVMV2R_V : VPseudo<VMV2R_V, V_M2, (outs VRM2:$vd), (ins VRM2:$vs2)>;
|
|
def PseudoVMV4R_V : VPseudo<VMV4R_V, V_M4, (outs VRM4:$vd), (ins VRM4:$vs2)>;
|
|
def PseudoVMV8R_V : VPseudo<VMV8R_V, V_M8, (outs VRM8:$vd), (ins VRM8:$vs2)>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 6. Configuration-Setting Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Pseudos.
|
|
let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
|
|
def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), []>;
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 7. Vector Loads and Stores
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Pseudos Unit-Stride Loads and Stores
|
|
foreach eew = EEWList in {
|
|
defm PseudoVLE # eew : VPseudoUSLoad;
|
|
defm PseudoVSE # eew : VPseudoUSStore;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12. Vector Integer Arithmetic Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.1. Vector Single-Width Integer Add and Subtract
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVADD : VPseudoBinaryV_VV_VX_VI;
|
|
defm PseudoVSUB : VPseudoBinaryV_VV_VX;
|
|
defm PseudoVRSUB : VPseudoBinaryV_VX_VI;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.2. Vector Widening Integer Add/Subtract
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVWADDU : VPseudoBinaryW_VV_VX;
|
|
defm PseudoVWSUBU : VPseudoBinaryW_VV_VX;
|
|
defm PseudoVWADD : VPseudoBinaryW_VV_VX;
|
|
defm PseudoVWSUB : VPseudoBinaryW_VV_VX;
|
|
defm PseudoVWADDU : VPseudoBinaryW_WV_WX;
|
|
defm PseudoVWSUBU : VPseudoBinaryW_WV_WX;
|
|
defm PseudoVWADD : VPseudoBinaryW_WV_WX;
|
|
defm PseudoVWSUB : VPseudoBinaryW_WV_WX;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVADC : VPseudoBinaryV_VM_XM_IM;
|
|
defm PseudoVMADC : VPseudoBinaryM_VM_XM_IM<"@earlyclobber $rd">;
|
|
defm PseudoVMADC : VPseudoBinaryM_V_X_I<"@earlyclobber $rd">;
|
|
|
|
defm PseudoVSBC : VPseudoBinaryV_VM_XM;
|
|
defm PseudoVMSBC : VPseudoBinaryM_VM_XM<"@earlyclobber $rd">;
|
|
defm PseudoVMSBC : VPseudoBinaryM_V_X<"@earlyclobber $rd">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.6. Vector Single-Width Bit Shift Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVSLL : VPseudoBinaryV_VV_VX_VI<uimm5>;
|
|
defm PseudoVSRL : VPseudoBinaryV_VV_VX_VI<uimm5>;
|
|
defm PseudoVSRA : VPseudoBinaryV_VV_VX_VI<uimm5>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.7. Vector Narrowing Integer Right Shift Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVNSRL : VPseudoBinaryV_WV_WX_WI;
|
|
defm PseudoVNSRA : VPseudoBinaryV_WV_WX_WI;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.9. Vector Integer Min/Max Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVMINU : VPseudoBinaryV_VV_VX;
|
|
defm PseudoVMIN : VPseudoBinaryV_VV_VX;
|
|
defm PseudoVMAXU : VPseudoBinaryV_VV_VX;
|
|
defm PseudoVMAX : VPseudoBinaryV_VV_VX;
|
|
|
|
} // Predicates = [HasStdExtV]
|
|
|
|
let Predicates = [HasStdExtV, HasStdExtF] in {
|
|
//===----------------------------------------------------------------------===//
|
|
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm PseudoVFADD : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
|
|
defm PseudoVFSUB : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
|
|
defm PseudoVFRSUB : VPseudoBinaryV_VX</*IsFloat=*/1>;
|
|
|
|
} // Predicates = [HasStdExtV, HasStdExtF]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
let Predicates = [HasStdExtV] in {
|
|
|
|
// Whole-register vector patterns.
|
|
|
|
// 7.4. Vector Unit-Stride Instructions
|
|
defm "" : VPatUSLoadStoreSDNodes<GPR>;
|
|
defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
|
|
|
|
// 12.1. Vector Single-Width Integer Add and Subtract
|
|
defm "" : VPatBinarySDNode<add, "PseudoVADD">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12. Vector Integer Arithmetic Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.1. Vector Single-Width Integer Add and Subtract
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>;
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>;
|
|
defm "" : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.2. Vector Widening Integer Add/Subtract
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU">;
|
|
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU">;
|
|
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD">;
|
|
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB">;
|
|
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU">;
|
|
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU">;
|
|
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD">;
|
|
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">;
|
|
defm "" : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">;
|
|
defm "" : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">;
|
|
|
|
defm "" : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">;
|
|
defm "" : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">;
|
|
defm "" : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.6. Vector Single-Width Bit Shift Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors,
|
|
uimm5>;
|
|
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,
|
|
uimm5>;
|
|
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
|
|
uimm5>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.7. Vector Narrowing Integer Right Shift Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL">;
|
|
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 12.9. Vector Integer Min/Max Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vminu", "PseudoVMINU", AllIntegerVectors>;
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmin", "PseudoVMIN", AllIntegerVectors>;
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmaxu", "PseudoVMAXU", AllIntegerVectors>;
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vmax", "PseudoVMAX", AllIntegerVectors>;
|
|
|
|
} // Predicates = [HasStdExtV]
|
|
|
|
let Predicates = [HasStdExtV, HasStdExtF] in {
|
|
//===----------------------------------------------------------------------===//
|
|
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>;
|
|
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>;
|
|
defm "" : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
|
|
|
|
} // Predicates = [HasStdExtV, HasStdExtF]
|