forked from OSchip/llvm-project
725 lines
26 KiB
C++
725 lines
26 KiB
C++
//===-- AArch64A57FPLoadBalancing.cpp - Balance FP ops statically on A57---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// For best-case performance on Cortex-A57, we should try to use a balanced
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// mix of odd and even D-registers when performing a critical sequence of
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// independent, non-quadword FP/ASIMD floating-point multiply or
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// multiply-accumulate operations.
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//
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// This pass attempts to detect situations where the register allocation may
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// adversely affect this load balancing and to change the registers used so as
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// to better utilize the CPU.
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//
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// Ideally we'd just take each multiply or multiply-accumulate in turn and
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// allocate it alternating even or odd registers. However, multiply-accumulates
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// are most efficiently performed in the same functional unit as their
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// accumulation operand. Therefore this pass tries to find maximal sequences
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// ("Chains") of multiply-accumulates linked via their accumulation operand,
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// and assign them all the same "color" (oddness/evenness).
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//
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// This optimization affects S-register and D-register floating point
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// multiplies and FMADD/FMAs, as well as vector (floating point only) muls and
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// FMADD/FMA. Q register instructions (and 128-bit vector instructions) are
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// not affected.
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/EquivalenceClasses.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-a57-fp-load-balancing"
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// Enforce the algorithm to use the scavenged register even when the original
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// destination register is the correct color. Used for testing.
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static cl::opt<bool>
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TransformAll("aarch64-a57-fp-load-balancing-force-all",
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cl::desc("Always modify dest registers regardless of color"),
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cl::init(false), cl::Hidden);
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// Never use the balance information obtained from chains - return a specific
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// color always. Used for testing.
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static cl::opt<unsigned>
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OverrideBalance("aarch64-a57-fp-load-balancing-override",
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cl::desc("Ignore balance information, always return "
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"(1: Even, 2: Odd)."),
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cl::init(0), cl::Hidden);
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//===----------------------------------------------------------------------===//
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// Helper functions
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// Is the instruction a type of multiply on 64-bit (or 32-bit) FPRs?
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static bool isMul(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case AArch64::FMULSrr:
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case AArch64::FNMULSrr:
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case AArch64::FMULDrr:
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case AArch64::FNMULDrr:
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return true;
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default:
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return false;
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}
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}
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// Is the instruction a type of FP multiply-accumulate on 64-bit (or 32-bit) FPRs?
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static bool isMla(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case AArch64::FMSUBSrrr:
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case AArch64::FMADDSrrr:
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case AArch64::FNMSUBSrrr:
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case AArch64::FNMADDSrrr:
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case AArch64::FMSUBDrrr:
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case AArch64::FMADDDrrr:
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case AArch64::FNMSUBDrrr:
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case AArch64::FNMADDDrrr:
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return true;
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default:
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return false;
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}
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}
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//===----------------------------------------------------------------------===//
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namespace {
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/// A "color", which is either even or odd. Yes, these aren't really colors
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/// but the algorithm is conceptually doing two-color graph coloring.
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enum class Color { Even, Odd };
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#ifndef NDEBUG
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static const char *ColorNames[2] = { "Even", "Odd" };
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#endif
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class Chain;
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class AArch64A57FPLoadBalancing : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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RegisterClassInfo RCI;
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public:
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static char ID;
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explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
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initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override {
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return "A57 FP Anti-dependency breaker";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool runOnBasicBlock(MachineBasicBlock &MBB);
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bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB,
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int &Balance);
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bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB);
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int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
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void scanInstruction(MachineInstr *MI, unsigned Idx,
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std::map<unsigned, Chain*> &Active,
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std::vector<std::unique_ptr<Chain>> &AllChains);
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void maybeKillChain(MachineOperand &MO, unsigned Idx,
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std::map<unsigned, Chain*> &RegChains);
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Color getColor(unsigned Register);
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Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L);
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};
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}
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char AArch64A57FPLoadBalancing::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE,
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"AArch64 A57 FP Load-Balancing", false, false)
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INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
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"AArch64 A57 FP Load-Balancing", false, false)
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namespace {
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/// A Chain is a sequence of instructions that are linked together by
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/// an accumulation operand. For example:
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///
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/// fmul def d0, ?
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/// fmla def d1, ?, ?, killed d0
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/// fmla def d2, ?, ?, killed d1
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///
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/// There may be other instructions interleaved in the sequence that
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/// do not belong to the chain. These other instructions must not use
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/// the "chain" register at any point.
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///
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/// We currently only support chains where the "chain" operand is killed
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/// at each link in the chain for simplicity.
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/// A chain has three important instructions - Start, Last and Kill.
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/// * The start instruction is the first instruction in the chain.
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/// * Last is the final instruction in the chain.
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/// * Kill may or may not be defined. If defined, Kill is the instruction
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/// where the outgoing value of the Last instruction is killed.
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/// This information is important as if we know the outgoing value is
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/// killed with no intervening uses, we can safely change its register.
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///
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/// Without a kill instruction, we must assume the outgoing value escapes
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/// beyond our model and either must not change its register or must
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/// create a fixup FMOV to keep the old register value consistent.
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///
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class Chain {
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public:
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/// The important (marker) instructions.
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MachineInstr *StartInst, *LastInst, *KillInst;
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/// The index, from the start of the basic block, that each marker
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/// appears. These are stored so we can do quick interval tests.
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unsigned StartInstIdx, LastInstIdx, KillInstIdx;
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/// All instructions in the chain.
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std::set<MachineInstr*> Insts;
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/// True if KillInst cannot be modified. If this is true,
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/// we cannot change LastInst's outgoing register.
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/// This will be true for tied values and regmasks.
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bool KillIsImmutable;
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/// The "color" of LastInst. This will be the preferred chain color,
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/// as changing intermediate nodes is easy but changing the last
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/// instruction can be more tricky.
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Color LastColor;
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Chain(MachineInstr *MI, unsigned Idx, Color C)
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: StartInst(MI), LastInst(MI), KillInst(nullptr),
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StartInstIdx(Idx), LastInstIdx(Idx), KillInstIdx(0),
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LastColor(C) {
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Insts.insert(MI);
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}
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/// Add a new instruction into the chain. The instruction's dest operand
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/// has the given color.
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void add(MachineInstr *MI, unsigned Idx, Color C) {
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LastInst = MI;
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LastInstIdx = Idx;
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LastColor = C;
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assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) &&
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"Chain: broken invariant. A Chain can only be killed after its last "
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"def");
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Insts.insert(MI);
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}
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/// Return true if MI is a member of the chain.
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bool contains(MachineInstr &MI) { return Insts.count(&MI) > 0; }
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/// Return the number of instructions in the chain.
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unsigned size() const {
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return Insts.size();
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}
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/// Inform the chain that its last active register (the dest register of
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/// LastInst) is killed by MI with no intervening uses or defs.
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void setKill(MachineInstr *MI, unsigned Idx, bool Immutable) {
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KillInst = MI;
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KillInstIdx = Idx;
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KillIsImmutable = Immutable;
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assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) &&
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"Chain: broken invariant. A Chain can only be killed after its last "
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"def");
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}
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/// Return the first instruction in the chain.
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MachineInstr *getStart() const { return StartInst; }
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/// Return the last instruction in the chain.
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MachineInstr *getLast() const { return LastInst; }
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/// Return the "kill" instruction (as set with setKill()) or NULL.
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MachineInstr *getKill() const { return KillInst; }
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/// Return an instruction that can be used as an iterator for the end
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/// of the chain. This is the maximum of KillInst (if set) and LastInst.
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MachineBasicBlock::iterator end() const {
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return ++MachineBasicBlock::iterator(KillInst ? KillInst : LastInst);
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}
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MachineBasicBlock::iterator begin() const { return getStart(); }
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/// Can the Kill instruction (assuming one exists) be modified?
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bool isKillImmutable() const { return KillIsImmutable; }
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/// Return the preferred color of this chain.
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Color getPreferredColor() {
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if (OverrideBalance != 0)
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return OverrideBalance == 1 ? Color::Even : Color::Odd;
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return LastColor;
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}
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/// Return true if this chain (StartInst..KillInst) overlaps with Other.
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bool rangeOverlapsWith(const Chain &Other) const {
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unsigned End = KillInst ? KillInstIdx : LastInstIdx;
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unsigned OtherEnd = Other.KillInst ?
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Other.KillInstIdx : Other.LastInstIdx;
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return StartInstIdx <= OtherEnd && Other.StartInstIdx <= End;
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}
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/// Return true if this chain starts before Other.
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bool startsBefore(const Chain *Other) const {
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return StartInstIdx < Other->StartInstIdx;
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}
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/// Return true if the group will require a fixup MOV at the end.
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bool requiresFixup() const {
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return (getKill() && isKillImmutable()) || !getKill();
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}
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/// Return a simple string representation of the chain.
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std::string str() const {
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std::string S;
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raw_string_ostream OS(S);
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OS << "{";
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StartInst->print(OS, /* SkipOpers= */true);
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OS << " -> ";
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LastInst->print(OS, /* SkipOpers= */true);
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if (KillInst) {
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OS << " (kill @ ";
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KillInst->print(OS, /* SkipOpers= */true);
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OS << ")";
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}
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OS << "}";
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return OS.str();
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}
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};
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} // end anonymous namespace
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//===----------------------------------------------------------------------===//
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bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
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if (skipFunction(F.getFunction()))
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return false;
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if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())
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return false;
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bool Changed = false;
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LLVM_DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n");
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MRI = &F.getRegInfo();
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TRI = F.getRegInfo().getTargetRegisterInfo();
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RCI.runOnMachineFunction(F);
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for (auto &MBB : F) {
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Changed |= runOnBasicBlock(MBB);
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}
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return Changed;
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}
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bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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LLVM_DEBUG(dbgs() << "Running on MBB: " << MBB
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<< " - scanning instructions...\n");
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// First, scan the basic block producing a set of chains.
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// The currently "active" chains - chains that can be added to and haven't
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// been killed yet. This is keyed by register - all chains can only have one
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// "link" register between each inst in the chain.
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std::map<unsigned, Chain*> ActiveChains;
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std::vector<std::unique_ptr<Chain>> AllChains;
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unsigned Idx = 0;
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for (auto &MI : MBB)
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scanInstruction(&MI, Idx++, ActiveChains, AllChains);
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LLVM_DEBUG(dbgs() << "Scan complete, " << AllChains.size()
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<< " chains created.\n");
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// Group the chains into disjoint sets based on their liveness range. This is
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// a poor-man's version of graph coloring. Ideally we'd create an interference
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// graph and perform full-on graph coloring on that, but;
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// (a) That's rather heavyweight for only two colors.
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// (b) We expect multiple disjoint interference regions - in practice the live
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// range of chains is quite small and they are clustered between loads
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// and stores.
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EquivalenceClasses<Chain*> EC;
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for (auto &I : AllChains)
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EC.insert(I.get());
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for (auto &I : AllChains)
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for (auto &J : AllChains)
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if (I != J && I->rangeOverlapsWith(*J))
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EC.unionSets(I.get(), J.get());
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LLVM_DEBUG(dbgs() << "Created " << EC.getNumClasses() << " disjoint sets.\n");
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// Now we assume that every member of an equivalence class interferes
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// with every other member of that class, and with no members of other classes.
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// Convert the EquivalenceClasses to a simpler set of sets.
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std::vector<std::vector<Chain*> > V;
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for (auto I = EC.begin(), E = EC.end(); I != E; ++I) {
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std::vector<Chain*> Cs(EC.member_begin(I), EC.member_end());
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if (Cs.empty()) continue;
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V.push_back(std::move(Cs));
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}
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// Now we have a set of sets, order them by start address so
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// we can iterate over them sequentially.
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llvm::sort(V,
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[](const std::vector<Chain *> &A, const std::vector<Chain *> &B) {
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return A.front()->startsBefore(B.front());
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});
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// As we only have two colors, we can track the global (BB-level) balance of
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// odds versus evens. We aim to keep this near zero to keep both execution
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// units fed.
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// Positive means we're even-heavy, negative we're odd-heavy.
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//
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// FIXME: If chains have interdependencies, for example:
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// mul r0, r1, r2
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// mul r3, r0, r1
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// We do not model this and may color each one differently, assuming we'll
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// get ILP when we obviously can't. This hasn't been seen to be a problem
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// in practice so far, so we simplify the algorithm by ignoring it.
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int Parity = 0;
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for (auto &I : V)
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Changed |= colorChainSet(std::move(I), MBB, Parity);
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return Changed;
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}
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Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
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std::vector<Chain*> &L) {
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if (L.empty())
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return nullptr;
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// We try and get the best candidate from L to color next, given that our
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// preferred color is "PreferredColor". L is ordered from larger to smaller
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// chains. It is beneficial to color the large chains before the small chains,
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// but if we can't find a chain of the maximum length with the preferred color,
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// we fuzz the size and look for slightly smaller chains before giving up and
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// returning a chain that must be recolored.
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// FIXME: Does this need to be configurable?
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const unsigned SizeFuzz = 1;
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unsigned MinSize = L.front()->size() - SizeFuzz;
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for (auto I = L.begin(), E = L.end(); I != E; ++I) {
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if ((*I)->size() <= MinSize) {
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// We've gone past the size limit. Return the previous item.
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Chain *Ch = *--I;
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L.erase(I);
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return Ch;
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}
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if ((*I)->getPreferredColor() == PreferredColor) {
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Chain *Ch = *I;
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L.erase(I);
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return Ch;
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}
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}
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// Bailout case - just return the first item.
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Chain *Ch = L.front();
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L.erase(L.begin());
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return Ch;
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}
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bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
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MachineBasicBlock &MBB,
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int &Parity) {
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bool Changed = false;
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LLVM_DEBUG(dbgs() << "colorChainSet(): #sets=" << GV.size() << "\n");
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// Sort by descending size order so that we allocate the most important
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// sets first.
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// Tie-break equivalent sizes by sorting chains requiring fixups before
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// those without fixups. The logic here is that we should look at the
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// chains that we cannot change before we look at those we can,
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// so the parity counter is updated and we know what color we should
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// change them to!
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// Final tie-break with instruction order so pass output is stable (i.e. not
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// dependent on malloc'd pointer values).
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llvm::sort(GV, [](const Chain *G1, const Chain *G2) {
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if (G1->size() != G2->size())
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return G1->size() > G2->size();
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if (G1->requiresFixup() != G2->requiresFixup())
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return G1->requiresFixup() > G2->requiresFixup();
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// Make sure startsBefore() produces a stable final order.
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assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) &&
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"Starts before not total order!");
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return G1->startsBefore(G2);
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});
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Color PreferredColor = Parity < 0 ? Color::Even : Color::Odd;
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while (Chain *G = getAndEraseNext(PreferredColor, GV)) {
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// Start off by assuming we'll color to our own preferred color.
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Color C = PreferredColor;
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if (Parity == 0)
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// But if we really don't care, use the chain's preferred color.
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C = G->getPreferredColor();
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LLVM_DEBUG(dbgs() << " - Parity=" << Parity
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<< ", Color=" << ColorNames[(int)C] << "\n");
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// If we'll need a fixup FMOV, don't bother. Testing has shown that this
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// happens infrequently and when it does it has at least a 50% chance of
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// slowing code down instead of speeding it up.
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if (G->requiresFixup() && C != G->getPreferredColor()) {
|
|
C = G->getPreferredColor();
|
|
LLVM_DEBUG(dbgs() << " - " << G->str()
|
|
<< " - not worthwhile changing; "
|
|
"color remains "
|
|
<< ColorNames[(int)C] << "\n");
|
|
}
|
|
|
|
Changed |= colorChain(G, C, MBB);
|
|
|
|
Parity += (C == Color::Even) ? G->size() : -G->size();
|
|
PreferredColor = Parity < 0 ? Color::Even : Color::Odd;
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
|
|
MachineBasicBlock &MBB) {
|
|
// Can we find an appropriate register that is available throughout the life
|
|
// of the chain? Simulate liveness backwards until the end of the chain.
|
|
LiveRegUnits Units(*TRI);
|
|
Units.addLiveOuts(MBB);
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
MachineBasicBlock::iterator ChainEnd = G->end();
|
|
while (I != ChainEnd) {
|
|
--I;
|
|
Units.stepBackward(*I);
|
|
}
|
|
|
|
// Check which register units are alive throughout the chain.
|
|
MachineBasicBlock::iterator ChainBegin = G->begin();
|
|
assert(ChainBegin != ChainEnd && "Chain should contain instructions");
|
|
do {
|
|
--I;
|
|
Units.accumulate(*I);
|
|
} while (I != ChainBegin);
|
|
|
|
// Make sure we allocate in-order, to get the cheapest registers first.
|
|
unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
|
|
auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
|
|
for (auto Reg : Ord) {
|
|
if (!Units.available(Reg))
|
|
continue;
|
|
if (C == getColor(Reg))
|
|
return Reg;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
|
|
MachineBasicBlock &MBB) {
|
|
bool Changed = false;
|
|
LLVM_DEBUG(dbgs() << " - colorChain(" << G->str() << ", "
|
|
<< ColorNames[(int)C] << ")\n");
|
|
|
|
// Try and obtain a free register of the right class. Without a register
|
|
// to play with we cannot continue.
|
|
int Reg = scavengeRegister(G, C, MBB);
|
|
if (Reg == -1) {
|
|
LLVM_DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n");
|
|
return false;
|
|
}
|
|
LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
|
|
|
|
std::map<unsigned, unsigned> Substs;
|
|
for (MachineInstr &I : *G) {
|
|
if (!G->contains(I) && (&I != G->getKill() || G->isKillImmutable()))
|
|
continue;
|
|
|
|
// I is a member of G, or I is a mutable instruction that kills G.
|
|
|
|
std::vector<unsigned> ToErase;
|
|
for (auto &U : I.operands()) {
|
|
if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
|
|
unsigned OrigReg = U.getReg();
|
|
U.setReg(Substs[OrigReg]);
|
|
if (U.isKill())
|
|
// Don't erase straight away, because there may be other operands
|
|
// that also reference this substitution!
|
|
ToErase.push_back(OrigReg);
|
|
} else if (U.isRegMask()) {
|
|
for (auto J : Substs) {
|
|
if (U.clobbersPhysReg(J.first))
|
|
ToErase.push_back(J.first);
|
|
}
|
|
}
|
|
}
|
|
// Now it's safe to remove the substs identified earlier.
|
|
for (auto J : ToErase)
|
|
Substs.erase(J);
|
|
|
|
// Only change the def if this isn't the last instruction.
|
|
if (&I != G->getKill()) {
|
|
MachineOperand &MO = I.getOperand(0);
|
|
|
|
bool Change = TransformAll || getColor(MO.getReg()) != C;
|
|
if (G->requiresFixup() && &I == G->getLast())
|
|
Change = false;
|
|
|
|
if (Change) {
|
|
Substs[MO.getReg()] = Reg;
|
|
MO.setReg(Reg);
|
|
|
|
Changed = true;
|
|
}
|
|
}
|
|
}
|
|
assert(Substs.size() == 0 && "No substitutions should be left active!");
|
|
|
|
if (G->getKill()) {
|
|
LLVM_DEBUG(dbgs() << " - Kill instruction seen.\n");
|
|
} else {
|
|
// We didn't have a kill instruction, but we didn't seem to need to change
|
|
// the destination register anyway.
|
|
LLVM_DEBUG(dbgs() << " - Destination register not changed.\n");
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
void AArch64A57FPLoadBalancing::scanInstruction(
|
|
MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain *> &ActiveChains,
|
|
std::vector<std::unique_ptr<Chain>> &AllChains) {
|
|
// Inspect "MI", updating ActiveChains and AllChains.
|
|
|
|
if (isMul(MI)) {
|
|
|
|
for (auto &I : MI->uses())
|
|
maybeKillChain(I, Idx, ActiveChains);
|
|
for (auto &I : MI->defs())
|
|
maybeKillChain(I, Idx, ActiveChains);
|
|
|
|
// Create a new chain. Multiplies don't require forwarding so can go on any
|
|
// unit.
|
|
unsigned DestReg = MI->getOperand(0).getReg();
|
|
|
|
LLVM_DEBUG(dbgs() << "New chain started for register "
|
|
<< printReg(DestReg, TRI) << " at " << *MI);
|
|
|
|
auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
|
|
ActiveChains[DestReg] = G.get();
|
|
AllChains.push_back(std::move(G));
|
|
|
|
} else if (isMla(MI)) {
|
|
|
|
// It is beneficial to keep MLAs on the same functional unit as their
|
|
// accumulator operand.
|
|
unsigned DestReg = MI->getOperand(0).getReg();
|
|
unsigned AccumReg = MI->getOperand(3).getReg();
|
|
|
|
maybeKillChain(MI->getOperand(1), Idx, ActiveChains);
|
|
maybeKillChain(MI->getOperand(2), Idx, ActiveChains);
|
|
if (DestReg != AccumReg)
|
|
maybeKillChain(MI->getOperand(0), Idx, ActiveChains);
|
|
|
|
if (ActiveChains.find(AccumReg) != ActiveChains.end()) {
|
|
LLVM_DEBUG(dbgs() << "Chain found for accumulator register "
|
|
<< printReg(AccumReg, TRI) << " in MI " << *MI);
|
|
|
|
// For simplicity we only chain together sequences of MULs/MLAs where the
|
|
// accumulator register is killed on each instruction. This means we don't
|
|
// need to track other uses of the registers we want to rewrite.
|
|
//
|
|
// FIXME: We could extend to handle the non-kill cases for more coverage.
|
|
if (MI->getOperand(3).isKill()) {
|
|
// Add to chain.
|
|
LLVM_DEBUG(dbgs() << "Instruction was successfully added to chain.\n");
|
|
ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg));
|
|
// Handle cases where the destination is not the same as the accumulator.
|
|
if (DestReg != AccumReg) {
|
|
ActiveChains[DestReg] = ActiveChains[AccumReg];
|
|
ActiveChains.erase(AccumReg);
|
|
}
|
|
return;
|
|
}
|
|
|
|
LLVM_DEBUG(
|
|
dbgs() << "Cannot add to chain because accumulator operand wasn't "
|
|
<< "marked <kill>!\n");
|
|
maybeKillChain(MI->getOperand(3), Idx, ActiveChains);
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "Creating new chain for dest register "
|
|
<< printReg(DestReg, TRI) << "\n");
|
|
auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
|
|
ActiveChains[DestReg] = G.get();
|
|
AllChains.push_back(std::move(G));
|
|
|
|
} else {
|
|
|
|
// Non-MUL or MLA instruction. Invalidate any chain in the uses or defs
|
|
// lists.
|
|
for (auto &I : MI->uses())
|
|
maybeKillChain(I, Idx, ActiveChains);
|
|
for (auto &I : MI->defs())
|
|
maybeKillChain(I, Idx, ActiveChains);
|
|
|
|
}
|
|
}
|
|
|
|
void AArch64A57FPLoadBalancing::
|
|
maybeKillChain(MachineOperand &MO, unsigned Idx,
|
|
std::map<unsigned, Chain*> &ActiveChains) {
|
|
// Given an operand and the set of active chains (keyed by register),
|
|
// determine if a chain should be ended and remove from ActiveChains.
|
|
MachineInstr *MI = MO.getParent();
|
|
|
|
if (MO.isReg()) {
|
|
|
|
// If this is a KILL of a current chain, record it.
|
|
if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
|
|
LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
|
|
<< "\n");
|
|
ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
|
|
}
|
|
ActiveChains.erase(MO.getReg());
|
|
|
|
} else if (MO.isRegMask()) {
|
|
|
|
for (auto I = ActiveChains.begin(), E = ActiveChains.end();
|
|
I != E;) {
|
|
if (MO.clobbersPhysReg(I->first)) {
|
|
LLVM_DEBUG(dbgs() << "Kill (regmask) seen for chain "
|
|
<< printReg(I->first, TRI) << "\n");
|
|
I->second->setKill(MI, Idx, /*Immutable=*/true);
|
|
ActiveChains.erase(I++);
|
|
} else
|
|
++I;
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
Color AArch64A57FPLoadBalancing::getColor(unsigned Reg) {
|
|
if ((TRI->getEncodingValue(Reg) % 2) == 0)
|
|
return Color::Even;
|
|
else
|
|
return Color::Odd;
|
|
}
|
|
|
|
// Factory function used by AArch64TargetMachine to add the pass to the passmanager.
|
|
FunctionPass *llvm::createAArch64A57FPLoadBalancing() {
|
|
return new AArch64A57FPLoadBalancing();
|
|
}
|