forked from OSchip/llvm-project
349 lines
11 KiB
C++
349 lines
11 KiB
C++
//===---------- MIRVRegNamerUtils.cpp - MIR VReg Renaming Utilities -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MIRVRegNamerUtils.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "mir-vregnamer-utils"
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namespace {
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// TypedVReg and VRType are used to tell the renamer what to do at points in a
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// sequence of values to be renamed. A TypedVReg can either contain
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// an actual VReg, a FrameIndex, or it could just be a barrier for the next
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// candidate (side-effecting instruction). This tells the renamer to increment
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// to the next vreg name, or to skip modulo some skip-gap value.
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enum VRType { RSE_Reg = 0, RSE_FrameIndex, RSE_NewCandidate };
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class TypedVReg {
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VRType Type;
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Register Reg;
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public:
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TypedVReg(Register Reg) : Type(RSE_Reg), Reg(Reg) {}
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TypedVReg(VRType Type) : Type(Type), Reg(~0U) {
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assert(Type != RSE_Reg && "Expected a non-Register Type.");
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}
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bool isReg() const { return Type == RSE_Reg; }
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bool isFrameIndex() const { return Type == RSE_FrameIndex; }
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bool isCandidate() const { return Type == RSE_NewCandidate; }
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VRType getType() const { return Type; }
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Register getReg() const {
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assert(this->isReg() && "Expected a virtual or physical Register.");
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return Reg;
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}
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};
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/// Here we find our candidates. What makes an interesting candidate?
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/// A candidate for a canonicalization tree root is normally any kind of
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/// instruction that causes side effects such as a store to memory or a copy to
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/// a physical register or a return instruction. We use these as an expression
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/// tree root that we walk in order to build a canonical walk which should
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/// result in canonical vreg renaming.
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std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
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std::vector<MachineInstr *> Candidates;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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for (auto II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
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MachineInstr *MI = &*II;
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bool DoesMISideEffect = false;
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if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
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const Register Dst = MI->getOperand(0).getReg();
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DoesMISideEffect |= !Register::isVirtualRegister(Dst);
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for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
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if (DoesMISideEffect)
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break;
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DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
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}
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}
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if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
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continue;
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LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
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Candidates.push_back(MI);
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}
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return Candidates;
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}
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void doCandidateWalk(std::vector<TypedVReg> &VRegs,
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std::queue<TypedVReg> &RegQueue,
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std::vector<MachineInstr *> &VisitedMIs,
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const MachineBasicBlock *MBB) {
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const MachineFunction &MF = *MBB->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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while (!RegQueue.empty()) {
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auto TReg = RegQueue.front();
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RegQueue.pop();
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if (TReg.isFrameIndex()) {
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LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
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VRegs.push_back(TypedVReg(RSE_FrameIndex));
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continue;
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}
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assert(TReg.isReg() && "Expected vreg or physreg.");
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Register Reg = TReg.getReg();
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if (Register::isVirtualRegister(Reg)) {
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LLVM_DEBUG({
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dbgs() << "Popping vreg ";
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MRI.def_begin(Reg)->dump();
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dbgs() << "\n";
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});
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if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
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return TR.isReg() && TR.getReg() == Reg;
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})) {
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VRegs.push_back(TypedVReg(Reg));
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}
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} else {
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LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
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VRegs.push_back(TypedVReg(Reg));
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continue;
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}
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for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
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MachineInstr *Def = RI->getParent();
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if (Def->getParent() != MBB)
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continue;
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if (llvm::any_of(VisitedMIs,
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[&](const MachineInstr *VMI) { return Def == VMI; })) {
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break;
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}
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LLVM_DEBUG({
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dbgs() << "\n========================\n";
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dbgs() << "Visited MI: ";
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Def->dump();
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dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
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dbgs() << "\n========================\n";
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});
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VisitedMIs.push_back(Def);
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for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
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MachineOperand &MO = Def->getOperand(I);
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if (MO.isFI()) {
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LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
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RegQueue.push(TypedVReg(RSE_FrameIndex));
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}
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if (!MO.isReg())
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continue;
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RegQueue.push(TypedVReg(MO.getReg()));
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}
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}
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}
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}
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std::map<unsigned, unsigned>
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getVRegRenameMap(const std::vector<TypedVReg> &VRegs,
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const std::vector<Register> &renamedInOtherBB,
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MachineRegisterInfo &MRI, NamedVRegCursor &NVC) {
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std::map<unsigned, unsigned> VRegRenameMap;
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bool FirstCandidate = true;
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for (auto &vreg : VRegs) {
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if (vreg.isFrameIndex()) {
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// We skip one vreg for any frame index because there is a good chance
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// (especially when comparing SelectionDAG to GlobalISel generated MIR)
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// that in the other file we are just getting an incoming vreg that comes
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// from a copy from a frame index. So it's safe to skip by one.
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unsigned LastRenameReg = NVC.incrementVirtualVReg();
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(void)LastRenameReg;
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LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
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continue;
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} else if (vreg.isCandidate()) {
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// After the first candidate, for every subsequent candidate, we skip mod
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// 10 registers so that the candidates are more likely to start at the
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// same vreg number making it more likely that the canonical walk from the
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// candidate insruction. We don't need to skip from the first candidate of
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// the BasicBlock because we already skip ahead several vregs for each BB.
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unsigned LastRenameReg = NVC.getVirtualVReg();
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if (FirstCandidate)
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NVC.incrementVirtualVReg(LastRenameReg % 10);
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FirstCandidate = false;
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continue;
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} else if (!Register::isVirtualRegister(vreg.getReg())) {
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unsigned LastRenameReg = NVC.incrementVirtualVReg();
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(void)LastRenameReg;
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LLVM_DEBUG({
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dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
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});
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continue;
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}
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auto Reg = vreg.getReg();
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if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
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LLVM_DEBUG(dbgs() << "Vreg " << Reg
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<< " already renamed in other BB.\n";);
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continue;
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}
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auto Rename = NVC.createVirtualRegister(Reg);
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if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
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LLVM_DEBUG(dbgs() << "Mapping vreg ";);
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if (MRI.reg_begin(Reg) != MRI.reg_end()) {
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LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
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} else {
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LLVM_DEBUG(dbgs() << Reg;);
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}
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LLVM_DEBUG(dbgs() << " to ";);
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if (MRI.reg_begin(Rename) != MRI.reg_end()) {
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LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
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} else {
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LLVM_DEBUG(dbgs() << Rename;);
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}
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LLVM_DEBUG(dbgs() << "\n";);
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VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
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}
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}
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return VRegRenameMap;
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}
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bool doVRegRenaming(std::vector<Register> &renamedInOtherBB,
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const std::map<unsigned, unsigned> &VRegRenameMap,
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MachineRegisterInfo &MRI) {
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bool Changed = false;
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for (auto I = VRegRenameMap.begin(), E = VRegRenameMap.end(); I != E; ++I) {
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auto VReg = I->first;
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auto Rename = I->second;
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renamedInOtherBB.push_back(Rename);
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std::vector<MachineOperand *> RenameMOs;
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for (auto &MO : MRI.reg_operands(VReg)) {
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RenameMOs.push_back(&MO);
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}
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for (auto *MO : RenameMOs) {
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Changed = true;
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MO->setReg(Rename);
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if (!MO->isDef())
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MO->setIsKill(false);
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}
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}
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return Changed;
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}
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bool renameVRegs(MachineBasicBlock *MBB,
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std::vector<Register> &renamedInOtherBB,
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NamedVRegCursor &NVC) {
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bool Changed = false;
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MachineFunction &MF = *MBB->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
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std::vector<MachineInstr *> VisitedMIs;
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llvm::copy(Candidates, std::back_inserter(VisitedMIs));
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std::vector<TypedVReg> VRegs;
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for (auto candidate : Candidates) {
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VRegs.push_back(TypedVReg(RSE_NewCandidate));
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std::queue<TypedVReg> RegQueue;
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// Here we walk the vreg operands of a non-root node along our walk.
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// The root nodes are the original candidates (stores normally).
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// These are normally not the root nodes (except for the case of copies to
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// physical registers).
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for (unsigned i = 1; i < candidate->getNumOperands(); i++) {
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if (candidate->mayStore() || candidate->isBranch())
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break;
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MachineOperand &MO = candidate->getOperand(i);
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if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
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continue;
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LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
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RegQueue.push(TypedVReg(MO.getReg()));
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}
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// Here we walk the root candidates. We start from the 0th operand because
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// the root is normally a store to a vreg.
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for (unsigned i = 0; i < candidate->getNumOperands(); i++) {
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if (!candidate->mayStore() && !candidate->isBranch())
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break;
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MachineOperand &MO = candidate->getOperand(i);
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// TODO: Do we want to only add vregs here?
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if (!MO.isReg() && !MO.isFI())
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continue;
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LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
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RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
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: TypedVReg(RSE_FrameIndex));
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}
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doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
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}
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// If we have populated no vregs to rename then bail.
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// The rest of this function does the vreg remaping.
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if (VRegs.size() == 0)
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return Changed;
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auto VRegRenameMap = getVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC);
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Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
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return Changed;
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}
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} // anonymous namespace
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void NamedVRegCursor::skipVRegs() {
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unsigned VRegGapIndex = 1;
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if (!virtualVRegNumber) {
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VRegGapIndex = 0;
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virtualVRegNumber = MRI.createIncompleteVirtualRegister();
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}
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const unsigned VR_GAP = (++VRegGapIndex * SkipGapSize);
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unsigned I = virtualVRegNumber;
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const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
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virtualVRegNumber = E;
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}
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unsigned NamedVRegCursor::createVirtualRegister(unsigned VReg) {
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if (!virtualVRegNumber)
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skipVRegs();
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std::string S;
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raw_string_ostream OS(S);
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OS << "namedVReg" << (virtualVRegNumber & ~0x80000000);
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OS.flush();
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virtualVRegNumber++;
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if (auto RC = MRI.getRegClassOrNull(VReg))
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return MRI.createVirtualRegister(RC, OS.str());
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return MRI.createGenericVirtualRegister(MRI.getType(VReg), OS.str());
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}
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bool NamedVRegCursor::renameVRegs(MachineBasicBlock *MBB) {
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return ::renameVRegs(MBB, RenamedInOtherBB, *this);
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}
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