llvm-project/llvm/test/CodeGen
Jinsong Ji 3d41a58eac [PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o
Summary:
This is found during https://reviews.llvm.org/D70758
All the other record forms are having suffix o at the end.
ANDIo8 and ANDISo8 are the only two that put o before 8.

This patch rename them to be consistent with others.

Reviewers: #powerpc, hfinkel, nemanjai, lei, steven.zhang, echristo, jhibbits, joerg

Reviewed By: jhibbits

Subscribers: wuzish, hiraditya, kbarton, shchenz, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70928
2019-12-09 19:21:34 +00:00
..
AArch64 [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates. 2019-12-06 16:24:57 -08:00
AMDGPU [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
ARC
ARM Revert "[PGO][PGSO] Instrument the code gen / target passes." 2019-12-06 12:17:32 -08:00
AVR
BPF [BPF] Support weak global variables for BTF 2019-12-07 08:58:19 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
Lanai
MIR [llvm] Fixing MIRVRegNamerUtils to properly handle 2+ MachineBasicBlocks. 2019-12-04 18:36:08 -05:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips Handle BUNDLE instructions in MipsAsmPrinter 2019-12-04 11:30:00 +00:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o 2019-12-09 19:21:34 +00:00
RISCV [RISCV] Fix mir-target-flags.ll 2019-12-09 13:51:08 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [FPEnv] Constrained FCmp intrinsics 2019-12-07 11:28:39 +01:00
Thumb Revert "ARM-Darwin: keep the frame register reserved even if not updated." 2019-12-06 10:59:26 -08:00
Thumb2 [ARM][MVE][Intrinsics] Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ, VQRDMULHQ intrinsics. 2019-12-09 17:41:47 +00:00
WebAssembly [WebAssembly] Fix miscompile of select with and 2019-11-15 16:22:01 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
X86 [X86] Fix prolog/epilog mismatch for stack protectors on win32-macho. 2019-12-06 14:44:56 -08:00
XCore