llvm-project/llvm/lib/CodeGen/SelectionDAG
Craig Topper 1a6c1ac686 [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.

Reviewed By: luismarques, RKSimon

Differential Revision: https://reviews.llvm.org/D97133
2021-02-21 11:13:36 -08:00
..
CMakeLists.txt llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
DAGCombiner.cpp [DAG] Match USUBSAT patterns through zext/trunc 2021-02-21 15:26:54 +00:00
FastISel.cpp Introduce llvm.noalias.decl intrinsic 2021-01-16 09:20:45 +01:00
FunctionLoweringInfo.cpp [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC. 2021-01-14 14:02:43 +00:00
InstrEmitter.cpp [CSSPGO] Pseudo probes for function calls. 2020-12-02 13:45:20 -08:00
InstrEmitter.h [CodeGen] Forward-declare TargetMachine (NFC) 2021-01-24 12:18:54 -08:00
LegalizeDAG.cpp [RISCV][LegalizeTypes] Try to expand BITREVERSE before promoting if the promoted BITREVERSE would expand anyway. 2021-02-15 12:33:16 -08:00
LegalizeFloatTypes.cpp [Legalizer] Promote result type in expanding FP_TO_XINT 2021-01-18 11:56:11 +08:00
LegalizeIntegerTypes.cpp [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add 2021-02-16 17:37:44 +00:00
LegalizeTypes.cpp [SelectionDAG] Use range-based for loops (NFC) 2021-02-09 22:14:30 -08:00
LegalizeTypes.h [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse 2021-02-15 13:39:43 +00:00
LegalizeTypesGeneric.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
LegalizeVectorOps.cpp Add intrinsics for saturating float to int casts 2020-12-18 11:09:41 +01:00
LegalizeVectorTypes.cpp [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse 2021-02-15 13:39:43 +00:00
ResourcePriorityQueue.cpp ResourcePriorityQueue.h - reduce unnecessary includes to forward declarations. NFC. 2020-05-26 19:22:14 +01:00
SDNodeDbgValue.h
ScheduleDAGFast.cpp [DebugInstrRef] Create DBG_INSTR_REFs in SelectionDAG 2020-10-14 14:24:08 +01:00
ScheduleDAGRRList.cpp Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" 2020-09-21 13:33:05 +02:00
ScheduleDAGSDNodes.cpp [SelectionDAG] Use range-based for loops (NFC) 2021-02-09 22:14:30 -08:00
ScheduleDAGSDNodes.h DAG: Use Register 2020-04-08 13:44:31 -04:00
ScheduleDAGVLIW.cpp [SelectionDAG] Use range-based for loops (NFC) 2021-02-09 22:14:30 -08:00
SelectionDAG.cpp [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM. 2021-02-21 11:13:36 -08:00
SelectionDAGAddressAnalysis.cpp [SelectionDAG] Avoid aliasing analysis if the object size is unknown. 2020-11-25 06:13:37 +08:00
SelectionDAGBuilder.cpp [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse 2021-02-15 13:39:43 +00:00
SelectionDAGBuilder.h [CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse 2021-02-15 13:39:43 +00:00
SelectionDAGDumper.cpp [CodeGen] Use range-based for loops (NFC) 2021-02-20 21:46:02 -08:00
SelectionDAGISel.cpp [TableGen][SelectionDAG] Improve efficiency of encoding negative immediates for isel's CheckInteger opcode. 2021-02-18 08:53:17 -08:00
SelectionDAGPrinter.cpp [SelectionDAG] Drop unnecessary const from a return type (NFC) 2021-02-07 09:49:33 -08:00
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp [Statepoint Lowering] Add an option to allow use gc values in regs for landing pad 2021-01-13 11:39:34 +07:00
StatepointLowering.h [Statepoint] Consolidate relocation type tracking [NFC] 2020-07-29 11:45:31 -07:00
TargetLowering.cpp [SelectionDAG][AArch64] Restrict matchUnaryPredicate to only handle SPLAT_VECTOR for scalable vectors. 2021-02-16 09:22:46 -08:00