forked from OSchip/llvm-project
136 lines
5.2 KiB
LLVM
136 lines
5.2 KiB
LLVM
; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s
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; RUN: opt %loadPolly -polly-ast -analyze < %s | FileCheck %s --check-prefix=AST
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;
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; void f(int *A, int N) {
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; for (int i = 0; i < N; i++)
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; switch (i % 4) {
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; case 0:
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; A[i] += 1;
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; case 1:
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; A[i] += 2;
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; break;
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; case 2:
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; A[i] += 3;
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; case 3:
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; A[i] += 4;
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; break;
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; }
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; }
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; CHECK: Statements {
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; CHECK-NEXT: Stmt_sw_bb
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] : 4*floor((i0)/4) = i0 and 0 <= i0 < N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> [i0, 2] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: Stmt_sw_bb_1
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] : 0 <= i0 < N and 4*floor((2 + i0)/4) <= i0 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> [i0, 3] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: Stmt_sw_bb_5
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] : 4*floor((-2 + i0)/4) = -2 + i0 and 0 <= i0 < N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> [i0, 0] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: Stmt_sw_bb_9
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] : 0 <= i0 < N and 4*floor((i0)/4) <= -2 + i0 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> [i0, 1] };
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; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
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; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> MemRef_A[i0] };
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; CHECK-NEXT: }
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; AST: if (1)
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;
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; AST: for (int c0 = 0; c0 < N; c0 += 1) {
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; AST-NEXT: if ((c0 - 2) % 4 == 0)
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; AST-NEXT: Stmt_sw_bb_5(c0);
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; AST-NEXT: if (c0 % 4 >= 2) {
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; AST-NEXT: Stmt_sw_bb_9(c0);
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; AST-NEXT: } else {
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; AST-NEXT: if (c0 % 4 == 0)
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; AST-NEXT: Stmt_sw_bb(c0);
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; AST-NEXT: Stmt_sw_bb_1(c0);
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; AST-NEXT: }
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; AST-NEXT: }
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;
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; AST: else
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; AST-NEXT: { /* original code */ }
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32* %A, i32 %N) {
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entry:
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%tmp = sext i32 %N to i64
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
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%cmp = icmp slt i64 %indvars.iv, %tmp
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%tmp1 = trunc i64 %indvars.iv to i32
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%rem = srem i32 %tmp1, 4
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switch i32 %rem, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.5
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i32 3, label %sw.bb.9
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]
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sw.bb: ; preds = %for.body
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%arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp2 = load i32, i32* %arrayidx, align 4
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%add = add nsw i32 %tmp2, 1
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store i32 %add, i32* %arrayidx, align 4
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br label %sw.bb.1
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sw.bb.1: ; preds = %sw.bb, %for.body
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%arrayidx3 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp3 = load i32, i32* %arrayidx3, align 4
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%add4 = add nsw i32 %tmp3, 2
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store i32 %add4, i32* %arrayidx3, align 4
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br label %sw.epilog
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sw.bb.5: ; preds = %for.body
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%arrayidx7 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp4 = load i32, i32* %arrayidx7, align 4
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%add8 = add nsw i32 %tmp4, 3
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store i32 %add8, i32* %arrayidx7, align 4
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br label %sw.bb.9
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sw.bb.9: ; preds = %sw.bb.5, %for.body
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%arrayidx11 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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%tmp5 = load i32, i32* %arrayidx11, align 4
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%add12 = add nsw i32 %tmp5, 4
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store i32 %add12, i32* %arrayidx11, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.9, %sw.bb.1, %for.body
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br label %for.inc
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for.inc: ; preds = %sw.epilog
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret void
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}
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