llvm-project/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir

87 lines
2.3 KiB
YAML

# RUN: llc -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"
define void @ScavengeForFrameWithoutOffset() { ret void }
...
---
name: ScavengeForFrameWithoutOffset
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, offset: 0, size: 32, alignment: 8 }
body: |
bb.0:
liveins: %d16_d17_d18_d19
%x0 = COPY %xzr
%x1 = COPY %xzr
%x2 = COPY %xzr
%x3 = COPY %xzr
%x4 = COPY %xzr
%x5 = COPY %xzr
%x6 = COPY %xzr
%x7 = COPY %xzr
%x8 = COPY %xzr
%x9 = COPY %xzr
%x10 = COPY %xzr
%x11 = COPY %xzr
%x12 = COPY %xzr
%x13 = COPY %xzr
%x14 = COPY %xzr
%x15 = COPY %xzr
%x16 = COPY %xzr
%x17 = COPY %xzr
%x18 = COPY %xzr
%x19 = COPY %xzr
%x20 = COPY %xzr
%x21 = COPY %xzr
%x22 = COPY %xzr
%x23 = COPY %xzr
%x24 = COPY %xzr
%x25 = COPY %xzr
%x26 = COPY %xzr
%x27 = COPY %xzr
%x28 = COPY %xzr
%fp = COPY %xzr
%lr = COPY %xzr
ST1Fourv1d killed %d16_d17_d18_d19, %stack.0 :: (store 32 into %stack.0, align 8)
; CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1)
; CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0
; CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8)
; CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1)
HINT 0, implicit %x0
HINT 0, implicit %x1
HINT 0, implicit %x2
HINT 0, implicit %x3
HINT 0, implicit %x4
HINT 0, implicit %x5
HINT 0, implicit %x6
HINT 0, implicit %x7
HINT 0, implicit %x8
HINT 0, implicit %x9
HINT 0, implicit %x10
HINT 0, implicit %x11
HINT 0, implicit %x12
HINT 0, implicit %x13
HINT 0, implicit %x14
HINT 0, implicit %x15
HINT 0, implicit %x16
HINT 0, implicit %x17
HINT 0, implicit %x18
HINT 0, implicit %x19
HINT 0, implicit %x20
HINT 0, implicit %x21
HINT 0, implicit %x22
HINT 0, implicit %x23
HINT 0, implicit %x24
HINT 0, implicit %x25
HINT 0, implicit %x26
HINT 0, implicit %x27
HINT 0, implicit %x28
HINT 0, implicit %fp
HINT 0, implicit %lr
RET_ReallyLR
...