forked from OSchip/llvm-project
daa4b6fbd9
Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164 |
||
|---|---|---|
| .. | ||
| abiflags.s | ||
| invalid-64.s | ||
| invalid.s | ||
| set-msa-directive-bad.s | ||
| set-msa-directive.s | ||
| test_2r.s | ||
| test_2r_msa64.s | ||
| test_2rf.s | ||
| test_3r.s | ||
| test_3rf.s | ||
| test_bit.s | ||
| test_cbranch.s | ||
| test_ctrlregs.s | ||
| test_dlsa.s | ||
| test_elm.s | ||
| test_elm_insert.s | ||
| test_elm_insert_msa64.s | ||
| test_elm_insve.s | ||
| test_elm_msa64.s | ||
| test_i5.s | ||
| test_i8.s | ||
| test_i10.s | ||
| test_lsa.s | ||
| test_mi10.s | ||
| test_vec.s | ||