Kito Cheng cc35161dc7 [RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters ... Those two TTI hooks are used during vectorization for calculating register pressure, the default implementation isn't consider for LMUL, and that's also definitly wrong value for register number (all register class are 8 registers). So in this patch we tried to: 1. Calculate right register usage for vector type and scalar type. 2. Return right number of register for general purpose register and vector register. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D116890		2022-01-17 15:27:54 +08:00
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lit.local.cfg	…
masked_gather_scatter.ll	[LV] Update test that was missed in e844f05397.	2021-10-18 18:23:00 +01:00
reg-usage.ll	[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters	2022-01-17 15:27:54 +08:00
riscv-interleaved.ll	Mark test as requiring asserts.	2021-06-01 02:01:01 -07:00
riscv-unroll.ll	[RISCV] Add a command line option to control the LMUL used by TTI's getRegisterBitWidth.	2022-01-07 20:02:10 -08:00
scalable-reductions.ll	…
scalable-vf-hint.ll	…
unroll-in-loop-vectorizer.ll	[RISCV] Disable interleaving scalar loops in the loop vectorizer.	2021-12-23 08:37:24 -06:00