forked from OSchip/llvm-project
267 lines
6.4 KiB
YAML
267 lines
6.4 KiB
YAML
# RUN: llc -run-pass implicit-null-checks -mtriple=x86_64-apple-macosx -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx"
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;; Positive test
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define i32 @imp_null_check_with_bitwise_op_0(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test. The regalloc is such that we cannot hoist the
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;; instruction materializing 2200000 into %eax
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define i32 @imp_null_check_with_bitwise_op_1(i32* %x, i32 %val, i32* %ptr) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 undef
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test: IR is identical to
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;; @imp_null_check_with_bitwise_op_0 but MIR differs.
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define i32 @imp_null_check_with_bitwise_op_2(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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;; Negative test: IR is identical to
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;; @imp_null_check_with_bitwise_op_0 but MIR differs.
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define i32 @imp_null_check_with_bitwise_op_3(i32* %x, i32 %val) {
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entry:
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br i1 undef, label %is_null, label %not_null, !make.implicit !0
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is_null:
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ret i32 42
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not_null:
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br i1 undef, label %ret_100, label %ret_200
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ret_100:
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ret i32 100
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ret_200:
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ret i32 200
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}
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!0 = !{}
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...
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---
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name: imp_null_check_with_bitwise_op_0
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# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
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alignment: 4
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allVRegsAllocated: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%rdi' }
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- { reg: '%esi' }
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# CHECK: bb.0.entry:
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# CHECK: %eax = MOV32ri 2200000
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# CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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# CHECK-NEXT: JMP_1 %bb.1.not_null
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body: |
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bb.0.entry:
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successors: %bb.3.is_null, %bb.1.not_null
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liveins: %esi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.3.is_null, implicit %eflags
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bb.1.not_null:
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successors: %bb.4.ret_100, %bb.2.ret_200
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liveins: %esi, %rdi
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%eax = MOV32ri 2200000
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%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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CMP32rr killed %eax, killed %esi, implicit-def %eflags
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JE_1 %bb.4.ret_100, implicit %eflags
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bb.2.ret_200:
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%eax = MOV32ri 200
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RET 0, %eax
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bb.3.is_null:
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%eax = MOV32ri 42
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RET 0, %eax
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bb.4.ret_100:
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%eax = MOV32ri 100
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RET 0, %eax
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...
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---
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name: imp_null_check_with_bitwise_op_1
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alignment: 4
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%rdi' }
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- { reg: '%esi' }
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- { reg: '%rdx' }
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# CHECK: bb.0.entry:
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# CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
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# CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags
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# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
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body: |
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bb.0.entry:
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successors: %bb.3.is_null, %bb.1.not_null
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liveins: %esi, %rdi, %rdx
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%eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.3.is_null, implicit %eflags
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bb.1.not_null:
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successors: %bb.4.ret_100, %bb.2.ret_200
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liveins: %esi, %rdi
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%eax = MOV32ri 2200000
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%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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CMP32rr killed %eax, killed %esi, implicit-def %eflags
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JE_1 %bb.4.ret_100, implicit %eflags
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bb.2.ret_200:
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successors: %bb.3.is_null
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%eax = MOV32ri 200
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bb.3.is_null:
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liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w
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RET 0, %eax
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bb.4.ret_100:
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%eax = MOV32ri 100
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RET 0, %eax
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...
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---
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name: imp_null_check_with_bitwise_op_2
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# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
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alignment: 4
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allVRegsAllocated: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%rdi' }
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- { reg: '%esi' }
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# CHECK: bb.0.entry:
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# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
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# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
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body: |
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bb.0.entry:
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successors: %bb.3.is_null, %bb.1.not_null
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liveins: %esi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.3.is_null, implicit %eflags
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bb.1.not_null:
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successors: %bb.4.ret_100, %bb.2.ret_200
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liveins: %esi, %rdi
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%eax = MOV32ri 2200000
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%eax = ADD32ri killed %eax, 100, implicit-def dead %eflags
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%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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CMP32rr killed %eax, killed %esi, implicit-def %eflags
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JE_1 %bb.4.ret_100, implicit %eflags
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bb.2.ret_200:
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%eax = MOV32ri 200
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RET 0, %eax
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bb.3.is_null:
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%eax = MOV32ri 42
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RET 0, %eax
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bb.4.ret_100:
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%eax = MOV32ri 100
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RET 0, %eax
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...
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---
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name: imp_null_check_with_bitwise_op_3
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# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
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alignment: 4
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allVRegsAllocated: true
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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liveins:
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- { reg: '%rdi' }
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- { reg: '%rsi' }
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# CHECK: bb.0.entry:
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# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
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# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
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body: |
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bb.0.entry:
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successors: %bb.3.is_null, %bb.1.not_null
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liveins: %rsi, %rdi
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TEST64rr %rdi, %rdi, implicit-def %eflags
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JE_1 %bb.3.is_null, implicit %eflags
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bb.1.not_null:
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successors: %bb.4.ret_100, %bb.2.ret_200
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liveins: %rsi, %rdi
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%rdi = MOV64ri 5000
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%rdi = AND64rm killed %rdi, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
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CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
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JE_1 %bb.4.ret_100, implicit %eflags
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bb.2.ret_200:
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%eax = MOV32ri 200
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RET 0, %eax
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bb.3.is_null:
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%eax = MOV32ri 42
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RET 0, %eax
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bb.4.ret_100:
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%eax = MOV32ri 100
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RET 0, %eax
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...
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