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AffineToStandard
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[mlir] Fix support for lowering non-32-bit affine reductions.
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2021-04-06 14:00:15 +02:00 |
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ArmSVEToLLVM
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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AsyncToLLVM
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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ComplexToLLVM
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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GPUCommon
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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GPUToNVVM
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[mlir] introduce data layout entry for index type
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2021-03-24 15:13:42 +01:00 |
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GPUToROCDL
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[mlir] introduce data layout entry for index type
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2021-03-24 15:13:42 +01:00 |
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GPUToSPIRV
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[mlir][spirv] Add utilities for push constant value
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2021-04-02 07:51:07 -04:00 |
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GPUToVulkan
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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LinalgToLLVM
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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LinalgToSPIRV
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[mlir][spirv] Add utilities for push constant value
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2021-04-02 07:51:07 -04:00 |
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LinalgToStandard
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[mlir][linalg] adding operation to access the iteration index of enclosing linalg ops.
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2021-04-12 13:37:17 +00:00 |
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OpenMPToLLVM
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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PDLToPDLInterp
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[mlir][pdl] Cast the OperationPosition to Position to fix MSVC miscompile
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2021-03-16 16:11:14 -07:00 |
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SCFToGPU
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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SCFToOpenMP
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Rename FrozenRewritePatternList -> FrozenRewritePatternSet; NFC.
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2021-03-22 17:40:45 -07:00 |
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SCFToSPIRV
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[mlir][spirv] Add utilities for push constant value
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2021-04-02 07:51:07 -04:00 |
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SCFToStandard
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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SPIRVToLLVM
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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ShapeToStandard
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Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator
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2021-03-25 03:59:03 +00:00 |
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StandardToLLVM
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[mlir] introduce data layout entry for index type
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2021-03-24 15:13:42 +01:00 |
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StandardToSPIRV
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[mlir][StandardToSPIRV] Add support for lowering math.powf to SPIR-V.
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2021-04-13 22:36:47 -07:00 |
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TosaToLinalg
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[mlir][tosa] Add conv2d lowering to linalg.conv2d operator for FP
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2021-04-13 13:26:02 -07:00 |
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TosaToSCF
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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TosaToStandard
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[PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC
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2021-03-22 17:20:50 -07:00 |
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VectorToLLVM
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[mlir] Rename AVX512 dialect to X86Vector
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2021-04-12 19:20:04 +02:00 |
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VectorToROCDL
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[mlir] Add "mask" operand to vector.transfer_read/write.
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2021-04-07 21:33:13 +09:00 |
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VectorToSCF
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[mlir] Add "mask" operand to vector.transfer_read/write.
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2021-04-07 21:33:13 +09:00 |
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VectorToSPIRV
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[mlir][spirv] Add utilities for push constant value
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2021-04-02 07:51:07 -04:00 |
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CMakeLists.txt
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[mlir] squash LLVM_AVX512 dialect into AVX512
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2021-03-10 13:07:26 +01:00 |
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PassDetail.h
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[mlir][amx] Add Intel AMX dialect (architectural-specific vector dialect)
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2021-03-15 17:59:05 -07:00 |
d9b03ef2e8