forked from OSchip/llvm-project
75 lines
2.7 KiB
C++
75 lines
2.7 KiB
C++
//===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on GCN processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include <list>
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namespace llvm {
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class MachineFunction;
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class MachineInstr;
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class ScheduleDAG;
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class SIInstrInfo;
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class SISubtarget;
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class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
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// This variable stores the instruction that has been emitted this cycle. It
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// will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
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// called.
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MachineInstr *CurrCycleInstr;
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std::list<MachineInstr*> EmittedInstrs;
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const MachineFunction &MF;
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const SISubtarget &ST;
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const SIInstrInfo &TII;
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int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard);
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int getWaitStatesSinceDef(unsigned Reg,
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function_ref<bool(MachineInstr *)> IsHazardDef =
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[](MachineInstr *) { return true; });
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int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
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int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
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int checkSMRDHazards(MachineInstr *SMRD);
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int checkVMEMHazards(MachineInstr* VMEM);
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int checkDPPHazards(MachineInstr *DPP);
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int checkDivFMasHazards(MachineInstr *DivFMas);
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int checkGetRegHazards(MachineInstr *GetRegInstr);
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int checkSetRegHazards(MachineInstr *SetRegInstr);
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int createsVALUHazard(const MachineInstr &MI);
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int checkVALUHazards(MachineInstr *VALU);
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int checkRWLaneHazards(MachineInstr *RWLane);
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int checkRFEHazards(MachineInstr *RFE);
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int checkAnyInstHazards(MachineInstr *MI);
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int checkReadM0Hazards(MachineInstr *SMovRel);
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public:
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GCNHazardRecognizer(const MachineFunction &MF);
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// We can only issue one instruction per cycle.
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bool atIssueLimit() const override { return true; }
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void EmitInstruction(SUnit *SU) override;
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void EmitInstruction(MachineInstr *MI) override;
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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void EmitNoop() override;
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unsigned PreEmitNoops(SUnit *SU) override;
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unsigned PreEmitNoops(MachineInstr *) override;
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void AdvanceCycle() override;
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void RecedeCycle() override;
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};
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} // end namespace llvm
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#endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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