forked from OSchip/llvm-project
f6e7ad5604
Resizing operations (e.g. sign extension) in DAG can go from any width to any other width, e.g. i8 -> i32. If the input and the result differ by a factor larger than 2, the operation cannot be legal in HVX, since the only two legal vector sizes in HVX are a single vector and a pair of vectors. To simplify the legalization, such operations are expanded into steps that only double/halve the type size, so that each such step can be fully legalized on its own. The complication is that DAG will automatically fold these steps back into one, e.g. sext(sext) -> sext. To prevent that new HexagonISD nodes are introduced: TL_EXTEND and TL_TRUNCATE. Once legalized, these nodes are replaced with the original opcodes. The type legalization is now common to aext/sext/zext/trunc and Hexagon- specific ssat/usat nodes. |
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| runtimes | ||
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| tools | ||
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| .clang-format | ||
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| CODE_OWNERS.TXT | ||
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| LICENSE.TXT | ||
| README.txt | ||
| RELEASE_TESTERS.TXT | ||
| configure | ||
| llvm.spec.in | ||
README.txt
The LLVM Compiler Infrastructure ================================ This directory and its subdirectories contain source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and runtime environments. LLVM is open source software. You may freely distribute it under the terms of the license agreement found in LICENSE.txt. Please see the documentation provided in docs/ for further assistance with LLVM, and in particular docs/GettingStarted.rst for getting started with LLVM and docs/README.txt for an overview of LLVM's documentation setup. If you are writing a package for LLVM, see docs/Packaging.rst for our suggestions.