llvm-project/llvm/test/CodeGen/MIR/AArch64
Francis Visoiu Mistrih e4718e84e8 [MIR] Add support for addrspace in MIR
Add support for printing / parsing the addrspace of a MachineMemOperand.

Fixes PR35970.

Differential Revision: https://reviews.llvm.org/D42502

llvm-svn: 323521
2018-01-26 11:47:28 +00:00
..
addrspace-memoperands.mir [MIR] Add support for addrspace in MIR 2018-01-26 11:47:28 +00:00
atomic-memoperands.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
cfi.mir [MIR] Add support for missing CFI directives 2017-12-15 15:17:18 +00:00
expected-target-flag-name.mir
generic-virtual-registers-error.mir CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
generic-virtual-registers-with-regbank-error.mir CodeGen: Refactor MIR parsing 2017-06-06 00:44:35 +00:00
intrinsics.mir
invalid-target-flag-name.mir
invalid-target-memoperands.mir [MIR] Add support for printing and parsing target MMO flags 2017-07-13 02:28:54 +00:00
lit.local.cfg
multiple-lhs-operands.mir
register-operand-bank.mir [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
stack-object-local-offset.mir MIR: Serialize CaleeSavedInfo Restored flag 2017-09-28 18:52:14 +00:00
swp.mir [mir] Print/Parse both MOLoad and MOStore when they occur together. 2017-11-28 18:57:02 +00:00
target-flags.mir
target-memoperands.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00