Sanjay Patel 2717252c92 [CostModel] add basic handling for FP maximum/minimum intrinsics ... This might be a regression for some ARM targets, but that should be changed in the target-specific overrides. There is apparently still no default lowering for these nodes, so I am assuming these intrinsics are not in common use. X86, PowerPC, and RISC-V for example, just crash given the most basic IR.		2020-11-22 13:43:53 -05:00
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AArch64	[AArch64] Add check for widening instruction for SVE.	2020-11-16 12:30:08 +00:00
AMDGPU	[AMDGPU][CostModel] Refine cost model for half- and quarter-rate instructions.	2020-10-24 19:53:08 +03:00
ARM	[CostModel] add basic handling for FP maximum/minimum intrinsics	2020-11-22 13:43:53 -05:00
PowerPC	Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"	2020-07-28 14:00:11 +00:00
RISCV	[CostModel] getCFInstrCost in getUserCost.	2020-06-15 09:28:46 +01:00
SystemZ	[SystemZ] Make sure not to call getZExtValue on a >64 bit constant.	2020-09-23 15:36:32 +02:00
X86	[CostModel] add basic handling for FP maximum/minimum intrinsics	2020-11-22 13:43:53 -05:00
free-intrinsics-datalayout.ll	[Annotation] Allows annotation to carry some additional constant arguments.	2020-10-26 10:50:05 +01:00
free-intrinsics-no_info.ll	[Annotation] Allows annotation to carry some additional constant arguments.	2020-10-26 10:50:05 +01:00
no_info.ll	…