forked from OSchip/llvm-project
873 lines
17 KiB
TableGen
873 lines
17 KiB
TableGen
//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes microMIPS32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MMR6Arch<string opstr> {
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string Arch = "micromipsr6";
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string BaseOpcode = opstr;
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}
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// Class used for microMIPS32r6 and microMIPS64r6 instructions.
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class MicroMipsR6Inst16 : PredicateControl {
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string DecoderNamespace = "MicroMipsR6";
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let InsnPredicates = [HasMicroMips32r6];
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}
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class BC16_FM_MM16R6 {
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bits<10> offset;
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bits<16> Inst;
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let Inst{15-10} = 0x33;
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let Inst{9-0} = offset;
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}
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class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
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bits<3> rs;
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bits<7> offset;
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bits<16> Inst;
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let Inst{15-10} = op;
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let Inst{9-7} = rs;
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let Inst{6-0} = offset;
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}
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class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
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bits<5> rs;
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bits<16> Inst;
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let Inst{15-10} = 0x11;
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let Inst{9-5} = rs;
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let Inst{4-0} = op;
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}
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class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
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bits<5> imm;
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bits<16> Inst;
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let Inst{15-10} = 0x11;
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let Inst{9-5} = imm;
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let Inst{4-0} = op;
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}
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class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
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bits<2> rt;
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bits<4> addr;
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bits<16> Inst;
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let Inst{15-10} = 0x11;
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let Inst{9-8} = rt;
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let Inst{7-4} = addr;
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let Inst{3-0} = funct;
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}
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class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rd;
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let Inst{15-12} = 0b0000;
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let Inst{11-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
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bits<21> addr;
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bits<5> hint;
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bits<32> Inst;
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let Inst{31-26} = opgroup;
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let Inst{25-21} = hint;
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let Inst{20-16} = addr{20-16};
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let Inst{15-12} = funct;
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let Inst{11-0} = addr{11-0};
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}
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class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0;
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let Inst{9-0} = funct;
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}
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class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm16;
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}
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class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
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bits<21> addr;
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bits<5> hint;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = hint;
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let Inst{20-16} = base;
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let Inst{15-12} = 0b1010;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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class LB32_FM_MMR6 : MipsR6Inst {
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bits<21> addr;
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bits<5> rt;
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bits<5> base = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b000111;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-0} = offset;
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}
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class LBU32_FM_MMR6 : MipsR6Inst {
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bits<21> addr;
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bits<5> rt;
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bits<5> base = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b000101;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-0} = offset;
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}
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class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
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bits<21> addr;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b011000;
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let Inst{25-21} = rt;
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let Inst{20-16} = addr{20-16};
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let Inst{15-12} = 0b0110;
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let Inst{11-9} = funct;
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let Inst{8-0} = addr{8-0};
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}
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class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rd;
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let Inst{20-16} = rt;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
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bits<5> rt;
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bits<19> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b011110;
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let Inst{25-21} = rt;
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let Inst{20-19} = funct;
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let Inst{18-0} = imm;
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}
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class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b011110;
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let Inst{25-21} = rt;
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let Inst{20-16} = funct;
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let Inst{15-0} = imm;
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}
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class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10} = 0;
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let Inst{9-0} = funct;
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}
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class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = 0;
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let Inst{20-16} = 0;
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let Inst{15-11} = op;
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let Inst{10-6} = 0;
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let Inst{5-0} = 0;
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}
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class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
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bits<5> rt;
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bits<5> rd;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rd;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_RDHWR_FM_MMR6 {
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bits<5> rt;
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bits<5> rs;
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bits<3> sel;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-14} = 0;
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let Inst{13-11} = sel;
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let Inst{10} = 0;
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let Inst{9-0} = 0b0111000000;
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}
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class POOL32A_SYNC_FM_MMR6 {
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bits<5> stype;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = 0;
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let Inst{20-16} = stype;
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let Inst{15-6} = 0b0110101101;
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let Inst{5-0} = 0b111100;
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}
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class POOL32I_SYNCI_FM_MMR6 {
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<16> immediate = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b010000;
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let Inst{25-21} = 0b01100;
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let Inst{20-16} = base;
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let Inst{15-0} = immediate;
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}
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class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = rt;
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let Inst{10-6} = 0b00001;
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let Inst{5-0} = funct;
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}
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class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> bp;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-9} = bp;
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let Inst{8-6} = 0b000;
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let Inst{5-0} = funct;
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}
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class AUI_FM_MMR6 : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = 0b000100;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-0} = imm;
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}
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class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> imm2;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{10-9} = imm2;
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let Inst{8-6} = 0b000;
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let Inst{5-0} = funct;
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}
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class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-0} = offset;
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}
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class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = 0b011000;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-12} = 0b1010;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = 0b011000;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-12} = 0b0110;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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class LOAD_WORD_FM_MMR6 {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<16> offset = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b111111;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-0} = offset;
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}
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class LOAD_UPPER_IMM_FM_MMR6 {
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = 0b000100;
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let Inst{25-21} = rt;
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let Inst{20-16} = 0;
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let Inst{15-0} = imm16;
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}
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class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rt;
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let Inst{20-16} = 0b00000;
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rt;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x00;
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let Inst{25-16} = 0x00;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x00;
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let Inst{25-17} = 0x00;
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let Inst{16-16} = 0x01;
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let Inst{15-6} = 0x3cd;
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let Inst{5-0} = 0x3c;
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}
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class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
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bits<10> code_1;
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bits<10> code_2;
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-16} = code_1;
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let Inst{15-6} = code_2;
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let Inst{5-0} = 0x07;
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}
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class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-21} = 0x0;
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let Inst{20-16} = 0x0;
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let Inst{15-11} = op;
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let Inst{10-6} = 0x0;
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let Inst{5-0} = 0x0;
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}
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class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<32> Inst;
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bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
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let Inst{31-26} = 0x00;
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let Inst{25-21} = 0x00;
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let Inst{20-16} = rt;
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let Inst{15-6} = funct;
|
|
let Inst{5-0} = 0x3c;
|
|
}
|
|
|
|
class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
|
|
bits<5> rd;
|
|
bits<5> rt;
|
|
bits<5> shamt;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0;
|
|
let Inst{25-21} = rd;
|
|
let Inst{20-16} = rt;
|
|
let Inst{15-11} = shamt;
|
|
let Inst{10} = rotate;
|
|
let Inst{9-0} = funct;
|
|
}
|
|
|
|
class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
|
|
bits<5> rt;
|
|
bits<21> addr;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = op;
|
|
let Inst{25-21} = rt;
|
|
let Inst{20-16} = addr{20-16};
|
|
let Inst{15-0} = addr{15-0};
|
|
}
|
|
|
|
class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
|
|
bits<3> funct> : MMR6Arch<instr_asm> {
|
|
bits<5> rt;
|
|
bits<21> addr;
|
|
bits<5> base = addr{20-16};
|
|
bits<9> offset = addr{8-0};
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = op;
|
|
let Inst{25-21} = rt;
|
|
let Inst{20-16} = base;
|
|
let Inst{15-12} = fmt;
|
|
let Inst{11-9} = funct;
|
|
let Inst{8-0} = offset;
|
|
}
|
|
|
|
class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15-11} = fd;
|
|
let Inst{10} = 0;
|
|
let Inst{9-8} = fmt;
|
|
let Inst{7-0} = funct;
|
|
}
|
|
|
|
class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15-11} = fd;
|
|
let Inst{10-9} = fmt;
|
|
let Inst{8-0} = funct;
|
|
}
|
|
|
|
class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14-13} = fmt;
|
|
let Inst{12-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15-11} = fd;
|
|
let Inst{10-9} = fmt;
|
|
let Inst{8-0} = funct;
|
|
}
|
|
|
|
class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15-11} = fd;
|
|
let Inst{10-6} = Cond.Value;
|
|
let Inst{5-0} = format;
|
|
}
|
|
|
|
class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14} = fmt;
|
|
let Inst{13-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14-13} = fmt;
|
|
let Inst{12-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14-13} = fmt;
|
|
let Inst{12-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14} = fmt;
|
|
let Inst{13-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
|
|
bits<3> rs;
|
|
bits<3> rt;
|
|
bits<3> rd;
|
|
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0b000001;
|
|
let Inst{9-7} = rs;
|
|
let Inst{6-4} = rt;
|
|
let Inst{3-1} = rd;
|
|
let Inst{0} = 0;
|
|
}
|
|
|
|
class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
|
|
bits<3> rt;
|
|
bits<3> rs;
|
|
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0b010001;
|
|
let Inst{9-7} = rt;
|
|
let Inst{6-4} = rs;
|
|
let Inst{3-0} = 0b0001;
|
|
}
|
|
|
|
class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
|
|
bits<3> rt;
|
|
bits<3> rs;
|
|
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0x11;
|
|
let Inst{9-7} = rt;
|
|
let Inst{6-4} = rs;
|
|
let Inst{3-0} = 0b0000;
|
|
}
|
|
|
|
class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
|
|
bits<3> rt;
|
|
bits<3> rs;
|
|
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0b010001;
|
|
let Inst{9-7} = rt;
|
|
let Inst{6-4} = rs;
|
|
let Inst{3-0} = op;
|
|
}
|
|
|
|
class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
|
|
bits<4> code_;
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0b010001;
|
|
let Inst{9-6} = code_;
|
|
let Inst{5-0} = op;
|
|
}
|
|
|
|
class POOL16A_SUBU16_FM_MMR6 {
|
|
bits<3> rs;
|
|
bits<3> rt;
|
|
bits<3> rd;
|
|
|
|
bits<16> Inst;
|
|
|
|
let Inst{15-10} = 0b000001;
|
|
let Inst{9-7} = rs;
|
|
let Inst{6-4} = rt;
|
|
let Inst{3-1} = rd;
|
|
let Inst{0} = 0b1;
|
|
}
|
|
|
|
class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
|
|
bits<5> rt;
|
|
bits<5> rs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x00;
|
|
let Inst{25-21} = rt;
|
|
let Inst{20-16} = rs;
|
|
let Inst{15-6} = funct;
|
|
let Inst{5-0} = 0x3c;
|
|
}
|
|
|
|
class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15} = 0;
|
|
let Inst{14} = fmt;
|
|
let Inst{13-6} = funct;
|
|
let Inst{5-0} = 0b111011;
|
|
}
|
|
|
|
class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = fs;
|
|
let Inst{20-16} = fd;
|
|
let Inst{15-11} = 0;
|
|
let Inst{10-9} = fmt;
|
|
let Inst{8-0} = 0b000100000;
|
|
}
|
|
|
|
class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> ft;
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = ft;
|
|
let Inst{20-16} = fs;
|
|
let Inst{15-11} = fd;
|
|
let Inst{10-9} = fmt;
|
|
let Inst{8-0} = funct;
|
|
}
|
|
|
|
class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<5> fs;
|
|
bits<5> fd;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0b010101;
|
|
let Inst{25-21} = fs;
|
|
let Inst{20-16} = fd;
|
|
let Inst{15-11} = 0b00000;
|
|
let Inst{10-9} = fmt;
|
|
let Inst{8-0} = funct;
|
|
}
|
|
|
|
class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
|
|
: MMR6Arch<instr_asm>, MipsR6Inst {
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x0;
|
|
let Inst{25-16} = 0x0;
|
|
let Inst{15-6} = funct;
|
|
let Inst{5-0} = 0b111100;
|
|
}
|