forked from OSchip/llvm-project
76 lines
2.2 KiB
C++
76 lines
2.2 KiB
C++
//===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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#include <cstdint>
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#include "llvm/Support/CommandLine.h"
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namespace llvm {
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struct InstrItinerary;
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struct InstrStage;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class Target;
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class Triple;
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class StringRef;
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class raw_ostream;
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class raw_pwrite_stream;
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extern Target TheHexagonTarget;
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extern cl::opt<bool> HexagonDisableCompound;
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extern cl::opt<bool> HexagonDisableDuplex;
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extern const InstrStage HexagonStages[];
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MCInstrInfo *createHexagonMCInstrInfo();
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MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &MCT);
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MCAsmBackend *createHexagonAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU);
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MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
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uint8_t OSABI, StringRef CPU);
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namespace HEXAGON_MC {
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StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
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}
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} // End llvm namespace
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// Define symbolic names for Hexagon registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "HexagonGenRegisterInfo.inc"
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// Defines symbolic names for the Hexagon instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "HexagonGenSubtargetInfo.inc"
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#endif
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