forked from OSchip/llvm-project
62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
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define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test1:
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; SSE2: # BB#0:
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movapd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test1:
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; SSE41: # BB#0:
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; SSE41-NEXT: retq
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%select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
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ret <4 x i32> %select
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}
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test2:
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; SSE2: # BB#0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test2:
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; SSE41: # BB#0:
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
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; SSE41-NEXT: retq
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%select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x i32> %A, <4 x i32> %B
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ret <4 x i32> %select
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}
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define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
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; SSE2-LABEL: test3:
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; SSE2: # BB#0:
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movapd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test3:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; SSE41-NEXT: retq
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%select = select <4 x i1><i1 true, i1 true, i1 false, i1 false>, <4 x float> %A, <4 x float> %B
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ret <4 x float> %select
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}
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define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
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; SSE2-LABEL: test4:
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; SSE2: # BB#0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test4:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE41-NEXT: retq
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%select = select <4 x i1><i1 false, i1 false, i1 true, i1 true>, <4 x float> %A, <4 x float> %B
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ret <4 x float> %select
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}
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