llvm-project/llvm/test/CodeGen
QingShan Zhang d84b320dfd [MacroFusion] Limit the max fused number as 2 to reduce the dependency
This is the example:

int foo(int a, int b, int c, int d) {
  return a + b + c + d;
}

And this is the Dependency Graph:
+------+       +------+       +------+       +------+
|  A   |       |  B   |       |  C   |       |  D   |
+--+--++       +---+--+       +--+---+       +--+---+
   ^  ^            ^  ^          ^              ^
   |  |            |  |          |              |
   |  |            |  |New1      +--------------+
   |  |            |  |          |
   |  |            |  |       +--+---+
   |  |New2        |  +-------+ ADD1 |
   |  |            |          +--+---+
   |  |            |    Fuse     ^
   |  |            +-------------+
   |  +------------+
   |               |
   |   Fuse     +--+---+
   +----------->+ ADD2 |
   |            +------+
+--+---+
| ADD3 |
+------+

We need also create an artificial edge from ADD1 to A if
https://reviews.llvm.org/D69998 is landed. That will force the Node A scheduled
before the ADD1 and ADD2. But in fact, it is ok to schedule the Node A
in-between ADD3 and ADD2, as ADD3 and ADD2 are NOT a fusion pair because
ADD2 has been matched to ADD1. We are creating these unnecessary dependency
edges that override the heuristics.

Differential Revision: https://reviews.llvm.org/D70066
2019-12-04 05:05:35 +00:00
..
AArch64 [MacroFusion] Limit the max fused number as 2 to reduce the dependency 2019-12-04 05:05:35 +00:00
AMDGPU AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics 2019-12-01 22:15:48 -08:00
ARC
ARM [GlobalISel]: Allow targets to override how to widen constants during legalization 2019-12-03 10:41:10 -08:00
AVR
BPF [BPF] add "llvm." prefix to BPF internally created globals 2019-11-25 21:34:46 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
Lanai
MIR [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips [GlobalISel]: Allow targets to override how to widen constants during legalization 2019-12-03 10:41:10 -08:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [PowerPC] folding rlwinm + rlwinm to rlwinm 2019-12-03 21:51:19 -05:00
RISCV [RISCV] Don't force Local Exec TLS for non-PIC 2019-12-03 22:04:54 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [SystemZ] Return the right offsets from getCalleeSavedSpillSlots(). 2019-11-25 19:03:05 +01:00
Thumb Revert "[ARM] Allocatable Global Register Variables for ARM" 2019-11-29 17:01:05 +00:00
Thumb2 [ARM] Add some VCMP folding and canonicalisation 2019-12-02 19:57:12 +00:00
WebAssembly [WebAssembly] Fix miscompile of select with and 2019-11-15 16:22:01 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
X86 [X86] Model DAZ and FTZ 2019-12-04 08:22:45 +08:00
XCore