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llvm-project/llvm/test/MC/RISCV/rvv
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ShihPo Hung 5cdb2e9860 [RISCV][MC] Fix nf encoding for vector ld/st whole register 
The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Reviewed By: craig.topper

Differential revision: https://reviews.llvm.org/D98185
 		2021-03-08 19:30:24 -08:00
..
add.s [RISCV] Update V instructions constraints to conform to v1.0 2021-01-22 01:15:55 +08:00
aliases.s [RISCV][MC] Fix nf encoding for vector ld/st whole register 2021-03-08 19:30:24 -08:00
and.s
…
clip.s
…
compare.s [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1' 2021-01-05 10:59:30 -08:00
convert.s [RISCV] Update V instructions constraints to conform to v1.0 2021-01-22 01:15:55 +08:00
div.s
…
ext.s
…
fadd.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fcompare.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fdiv.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fmacc.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fminmax.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fmul.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fmv.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fothers.s [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
freduction.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
fsub.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
invalid.s [RISCV] Change parseVTypeI function 2021-02-12 19:38:34 +08:00
load.s [RISCV][MC] Fix nf encoding for vector ld/st whole register 2021-03-08 19:30:24 -08:00
macc.s
…
mask.s
…
minmax.s
…
mul.s
…
mv.s
…
or.s
…
others.s [RISCV] Add new V instructions in v1.0-08a0b46. 2021-01-22 00:59:58 +08:00
reduction.s
…
shift.s [RISCV] Update V instructions constraints to conform to v1.0 2021-01-22 01:15:55 +08:00
sign-injection.s [RISCV] V does not imply F. 2020-12-17 10:57:36 +08:00
snippet.s [RISCV] Make LMUL field in VTYPE continuous. 2021-01-22 00:47:32 +08:00
store.s [RISCV][MC] Fix nf encoding for vector ld/st whole register 2021-03-08 19:30:24 -08:00
sub.s [RISCV] Update V instructions constraints to conform to v1.0 2021-01-22 01:15:55 +08:00
vsetvl.s [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
xor.s
…
zvamo.s [RISCV] add the MC layer support of riscv vector Zvamo extension 2020-08-27 14:11:38 +08:00
zvlsseg.s [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00