llvm-project/llvm/test/MC/Disassembler
Dmitry Preobrazhensky b181c7312e [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847

Differential Revision: https://reviews.llvm.org/D45097

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328988
2018-04-02 17:09:20 +00:00
..
AArch64 [AArch64] Fix spelling of ICH_ELRSR_EL2 system register 2018-02-06 09:39:04 +00:00
AMDGPU [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16 2018-04-02 17:09:20 +00:00
ARC [ARC] Add instruction subset for the ARC backend. 2017-12-02 05:25:17 +00:00
ARM [ARM]Decoding MSR with unpredictable destination register causes an assert 2018-03-06 15:21:19 +00:00
Hexagon [Hexagon] Remove trailing spaces, NFC 2017-11-22 20:43:00 +00:00
Lanai
Mips [mips] Add support for CRC ASE 2018-03-14 14:13:31 +00:00
PowerPC [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9. 2018-02-23 15:55:16 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
X86 [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168) 2018-02-17 14:58:16 +00:00
XCore