forked from OSchip/llvm-project
64 lines
2.0 KiB
YAML
64 lines
2.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_div() {
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entry:
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ret void
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}
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...
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---
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name: test_div
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2, $x3
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; CHECK-LABEL: name: test_div
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
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; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
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; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
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; CHECK: $w0 = COPY [[COPY2]](s32)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
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; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
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; CHECK: $w0 = COPY [[COPY3]](s32)
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%0(s64) = COPY $x0
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%1(s64) = COPY $x1
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%2(s8) = G_TRUNC %0
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%3(s8) = G_TRUNC %1
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%4(s8) = G_SDIV %2, %3
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%6:_(s32) = G_ANYEXT %4
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$w0 = COPY %6
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%5(s8) = G_UDIV %2, %3
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%7:_(s32) = G_ANYEXT %5
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$w0 = COPY %7
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...
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