forked from OSchip/llvm-project
605 lines
20 KiB
C++
605 lines
20 KiB
C++
//===----- HexagonShuffler.cpp - Instruction bundle shuffling -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the shuffling of insns inside a bundle according to the
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// packet formation rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hexagon-shuffle"
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#include "HexagonShuffler.h"
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <utility>
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using namespace llvm;
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namespace {
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// Insn shuffling priority.
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class HexagonBid {
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// The priority is directly proportional to how restricted the insn is based
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// on its flexibility to run on the available slots. So, the fewer slots it
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// may run on, the higher its priority.
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enum { MAX = 360360 }; // LCD of 1/2, 1/3, 1/4,... 1/15.
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unsigned Bid;
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public:
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HexagonBid() : Bid(0) {}
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HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; }
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// Check if the insn priority is overflowed.
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bool isSold() const { return (Bid >= MAX); }
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HexagonBid &operator+=(const HexagonBid &B) {
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Bid += B.Bid;
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return *this;
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}
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};
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// Slot shuffling allocation.
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class HexagonUnitAuction {
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HexagonBid Scores[HEXAGON_PACKET_SIZE];
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// Mask indicating which slot is unavailable.
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unsigned isSold : HEXAGON_PACKET_SIZE;
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public:
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HexagonUnitAuction(unsigned cs = 0) : isSold(cs){};
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// Allocate slots.
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bool bid(unsigned B) {
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// Exclude already auctioned slots from the bid.
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unsigned b = B & ~isSold;
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if (b) {
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for (unsigned i = 0; i < HEXAGON_PACKET_SIZE; ++i)
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if (b & (1 << i)) {
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// Request candidate slots.
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Scores[i] += HexagonBid(b);
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isSold |= Scores[i].isSold() << i;
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}
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return true;
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} else
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// Error if the desired slots are already full.
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return false;
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}
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};
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} // end anonymous namespace
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unsigned HexagonResource::setWeight(unsigned s) {
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const unsigned SlotWeight = 8;
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const unsigned MaskWeight = SlotWeight - 1;
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unsigned Units = getUnits();
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unsigned Key = ((1u << s) & Units) != 0;
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// Calculate relative weight of the insn for the given slot, weighing it the
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// heavier the more restrictive the insn is and the lowest the slots that the
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// insn may be executed in.
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if (Key == 0 || Units == 0 || (SlotWeight * s >= 32))
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return Weight = 0;
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unsigned Ctpop = countPopulation(Units);
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unsigned Cttz = countTrailingZeros(Units);
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Weight = (1u << (SlotWeight * s)) * ((MaskWeight - Ctpop) << Cttz);
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return Weight;
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}
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void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
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(*TUL)[HexagonII::TypeCVI_VA] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
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(*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VX_LATE] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2);
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(*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
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(*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
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(*TUL)[HexagonII::TypeCVI_VINLANESAT] =
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(CPU == "hexagonv60")
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? UnitsAndLanes(CVI_SHIFT, 1)
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: UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_LD] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0);
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(*TUL)[HexagonII::TypeCVI_VM_VP_LDU] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_VM_ST] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0);
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(*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4);
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}
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HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL,
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MCInstrInfo const &MCII, unsigned s,
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MCInst const *id)
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: HexagonResource(s), TUL(TUL) {
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unsigned T = HexagonMCInstrInfo::getType(MCII, *id);
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if (TUL->count(T)) {
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// For an HVX insn.
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Valid = true;
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setUnits((*TUL)[T].first);
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setLanes((*TUL)[T].second);
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setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad());
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setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore());
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} else {
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// For core insns.
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Valid = false;
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setUnits(0);
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setLanes(0);
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setLoad(false);
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setStore(false);
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}
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}
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struct CVIUnits {
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unsigned Units;
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unsigned Lanes;
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};
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typedef SmallVector<struct CVIUnits, 8> HVXInstsT;
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static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
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{
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for (unsigned i = 1; i < Lanes; ++i)
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startBit = (startBit << 1) | startBit;
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return startBit;
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}
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static bool checkHVXPipes(const HVXInstsT &hvxInsts, unsigned startIdx,
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unsigned usedUnits)
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{
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if (startIdx < hvxInsts.size()) {
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if (!hvxInsts[startIdx].Units)
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return checkHVXPipes(hvxInsts, startIdx + 1, usedUnits);
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for (unsigned b = 0x1; b <= 0x8; b <<= 1) {
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if ((hvxInsts[startIdx].Units & b) == 0)
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continue;
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unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes);
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if ((allBits & usedUnits) == 0) {
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if (checkHVXPipes(hvxInsts, startIdx + 1, usedUnits | allBits))
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return true;
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}
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}
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return false;
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}
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return true;
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}
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HexagonShuffler::HexagonShuffler(MCContext &Context, bool ReportErrors,
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MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI)
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: Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) {
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reset();
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HexagonCVIResource::SetupTUL(&TUL, STI.getCPU());
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}
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void HexagonShuffler::reset() {
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Packet.clear();
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BundleFlags = 0;
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}
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void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
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unsigned S) {
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HexagonInstr PI(&TUL, MCII, &ID, Extender, S);
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Packet.push_back(PI);
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}
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static struct {
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unsigned first;
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unsigned second;
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} jumpSlots[] = {{8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}};
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#define MAX_JUMP_SLOTS (sizeof(jumpSlots) / sizeof(jumpSlots[0]))
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/// Check that the packet is legal and enforce relative insn order.
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bool HexagonShuffler::check() {
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// Descriptive slot masks.
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const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2,
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slotThree = 0x8, // slotFirstJump = 0x8,
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slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
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// Highest slots for branches and stores used to keep their original order.
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// unsigned slotJump = slotFirstJump;
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unsigned slotLoadStore = slotFirstLoadStore;
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// Number of branches, solo branches, indirect branches.
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unsigned jumps = 0, jump1 = 0;
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// Number of memory operations, loads, solo loads, stores, solo stores, single
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// stores.
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unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
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// Number of duplex insns
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unsigned duplex = 0;
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// Number of insns restricting other insns in slot #1 to A type.
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unsigned onlyAin1 = 0;
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// Number of insns restricting any insn in slot #1, except A2_nop.
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unsigned onlyNo1 = 0;
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unsigned pSlot3Cnt = 0;
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unsigned nvstores = 0;
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unsigned memops = 0;
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unsigned deallocs = 0;
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iterator slot3ISJ = end();
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std::vector<iterator> foundBranches;
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unsigned reservedSlots = 0;
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// Collect information from the insns in the packet.
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
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MCInst const &ID = ISJ->getDesc();
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if (HexagonMCInstrInfo::isSoloAin1(MCII, ID))
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++onlyAin1;
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if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) {
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++pSlot3Cnt;
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slot3ISJ = ISJ;
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}
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reservedSlots |= HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID);
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if (HexagonMCInstrInfo::isCofMax1(MCII, ID))
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++jump1;
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switch (HexagonMCInstrInfo::getType(MCII, ID)) {
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case HexagonII::TypeS_2op:
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case HexagonII::TypeS_3op:
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case HexagonII::TypeALU64:
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break;
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case HexagonII::TypeJ:
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++jumps;
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foundBranches.push_back(ISJ);
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break;
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case HexagonII::TypeCVI_VM_VP_LDU:
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++onlyNo1;
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case HexagonII::TypeCVI_VM_LD:
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case HexagonII::TypeCVI_VM_TMP_LD:
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case HexagonII::TypeLD:
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++loads;
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++memory;
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if (ISJ->Core.getUnits() == slotSingleLoad ||
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HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU)
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++load0;
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if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) {
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++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
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foundBranches.push_back(ISJ);
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}
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break;
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case HexagonII::TypeCVI_VM_STU:
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++onlyNo1;
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case HexagonII::TypeCVI_VM_ST:
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case HexagonII::TypeCVI_VM_NEW_ST:
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case HexagonII::TypeST:
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++stores;
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++memory;
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if (ISJ->Core.getUnits() == slotSingleStore ||
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HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_STU)
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++store0;
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break;
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case HexagonII::TypeV4LDST:
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++loads;
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++stores;
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++store1;
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++memops;
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++memory;
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break;
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case HexagonII::TypeNCJ:
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++memory; // NV insns are memory-like.
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++jumps, ++jump1;
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foundBranches.push_back(ISJ);
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break;
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case HexagonII::TypeV2LDST:
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if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
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++loads;
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++memory;
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if (ISJ->Core.getUnits() == slotSingleLoad ||
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HexagonMCInstrInfo::getType(MCII, ID) ==
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HexagonII::TypeCVI_VM_VP_LDU)
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++load0;
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} else {
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assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore());
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++memory;
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++stores;
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if (HexagonMCInstrInfo::isNewValue(MCII, ID))
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++nvstores;
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}
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break;
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case HexagonII::TypeCR:
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// Legacy conditional branch predicated on a register.
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case HexagonII::TypeCJ:
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if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) {
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++jumps;
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foundBranches.push_back(ISJ);
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}
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break;
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case HexagonII::TypeDUPLEX: {
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++duplex;
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MCInst const &Inst0 = *ID.getOperand(0).getInst();
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MCInst const &Inst1 = *ID.getOperand(1).getInst();
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if (HexagonMCInstrInfo::isCofMax1(MCII, Inst0))
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++jump1;
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if (HexagonMCInstrInfo::isCofMax1(MCII, Inst1))
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++jump1;
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if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) {
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++jumps;
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foundBranches.push_back(ISJ);
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}
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if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) {
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++jumps;
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foundBranches.push_back(ISJ);
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}
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if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) {
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++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
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foundBranches.push_back(ISJ);
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}
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if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) {
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++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
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foundBranches.push_back(ISJ);
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}
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break;
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}
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}
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}
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// Check if the packet is legal.
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if ((load0 > 1 || store0 > 1) ||
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(duplex > 1 || (duplex && memory))) {
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reportError(llvm::Twine("invalid instruction packet"));
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return false;
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}
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if (jump1 && jumps > 1) {
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// Error if single branch with another branch.
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reportError(llvm::Twine("too many branches in packet"));
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return false;
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}
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if ((nvstores || memops) && stores > 1) {
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reportError(llvm::Twine("slot 0 instruction does not allow slot 1 store"));
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return false;
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}
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if (deallocs && stores) {
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reportError(llvm::Twine("slot 0 instruction does not allow slot 1 store"));
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return false;
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}
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// Modify packet accordingly.
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// TODO: need to reserve slots #0 and #1 for duplex insns.
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bool bOnlySlot3 = false;
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
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MCInst const &ID = ISJ->getDesc();
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if (!ISJ->Core.getUnits()) {
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// Error if insn may not be executed in any slot.
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return false;
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}
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// Exclude from slot #1 any insn but A2_nop.
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if (HexagonMCInstrInfo::getDesc(MCII, ID).getOpcode() != Hexagon::A2_nop)
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if (onlyNo1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
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// Exclude from slot #1 any insn but A-type.
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if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_2op &&
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HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_3op &&
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HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_ADDI)
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if (onlyAin1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
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// A single load must use slot #0.
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if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
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if (loads == 1 && loads == memory && memops == 0)
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// Pin the load to slot #0.
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
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}
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// A single store must use slot #0.
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if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) {
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if (!store0) {
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if (stores == 1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore);
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else if (stores > 1) {
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if (slotLoadStore < slotLastLoadStore) {
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// Error if no more slots available for stores.
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reportError(
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llvm::Twine("invalid instruction packet: too many stores"));
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return false;
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}
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// Pin the store to the highest slot available to it.
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
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// Update the next highest slot available to stores.
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slotLoadStore >>= 1;
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}
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}
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if (store1 && stores > 1) {
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// Error if a single store with another store.
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reportError(llvm::Twine("invalid instruction packet: too many stores"));
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return false;
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}
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}
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// flag if an instruction requires to be in slot 3
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if (ISJ->Core.getUnits() == slotThree)
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bOnlySlot3 = true;
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if (!ISJ->Core.getUnits()) {
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// Error if insn may not be executed in any slot.
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reportError(llvm::Twine("invalid instruction packet: out of slots"));
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return false;
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}
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}
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// preserve branch order
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bool validateSlots = true;
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if (jumps > 1) {
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if (foundBranches.size() > 2) {
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reportError(llvm::Twine("too many branches in packet"));
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return false;
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}
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// try all possible choices
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for (unsigned int i = 0; i < MAX_JUMP_SLOTS; ++i) {
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// validate first jump with this slot rule
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if (!(jumpSlots[i].first & foundBranches[0]->Core.getUnits()))
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continue;
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// validate second jump with this slot rule
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if (!(jumpSlots[i].second & foundBranches[1]->Core.getUnits()))
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continue;
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// both valid for this configuration, set new slot rules
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PacketSave = Packet;
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foundBranches[0]->Core.setUnits(jumpSlots[i].first);
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foundBranches[1]->Core.setUnits(jumpSlots[i].second);
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HexagonUnitAuction AuctionCore(reservedSlots);
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std::sort(begin(), end(), HexagonInstr::lessCore);
|
|
|
|
// see if things ok with that instruction being pinned to slot "slotJump"
|
|
bool bFail = false;
|
|
for (iterator I = begin(); I != end() && bFail != true; ++I)
|
|
if (!AuctionCore.bid(I->Core.getUnits()))
|
|
bFail = true;
|
|
|
|
// if yes, great, if not then restore original slot mask
|
|
if (!bFail) {
|
|
validateSlots = false; // all good, no need to re-do auction
|
|
break;
|
|
} else
|
|
// restore original values
|
|
Packet = PacketSave;
|
|
}
|
|
if (validateSlots == true) {
|
|
reportError(llvm::Twine("invalid instruction packet: out of slots"));
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (jumps <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 &&
|
|
slot3ISJ != end()) {
|
|
validateSlots = true;
|
|
// save off slot mask of instruction marked with A_PREFER_SLOT3
|
|
// and then pin it to slot #3
|
|
unsigned saveUnits = slot3ISJ->Core.getUnits();
|
|
slot3ISJ->Core.setUnits(saveUnits & slotThree);
|
|
|
|
HexagonUnitAuction AuctionCore(reservedSlots);
|
|
std::sort(begin(), end(), HexagonInstr::lessCore);
|
|
|
|
// see if things ok with that instruction being pinned to slot #3
|
|
bool bFail = false;
|
|
for (iterator I = begin(); I != end() && bFail != true; ++I)
|
|
if (!AuctionCore.bid(I->Core.getUnits()))
|
|
bFail = true;
|
|
|
|
// if yes, great, if not then restore original slot mask
|
|
if (!bFail)
|
|
validateSlots = false; // all good, no need to re-do auction
|
|
else
|
|
for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
|
|
MCInst const &ID = ISJ->getDesc();
|
|
if (HexagonMCInstrInfo::prefersSlot3(MCII, ID))
|
|
ISJ->Core.setUnits(saveUnits);
|
|
}
|
|
}
|
|
|
|
// Check if any slot, core or CVI, is over-subscribed.
|
|
// Verify the core slot subscriptions.
|
|
if (validateSlots) {
|
|
HexagonUnitAuction AuctionCore(reservedSlots);
|
|
|
|
std::sort(begin(), end(), HexagonInstr::lessCore);
|
|
|
|
for (iterator I = begin(); I != end(); ++I)
|
|
if (!AuctionCore.bid(I->Core.getUnits())) {
|
|
reportError(llvm::Twine("invalid instruction packet: slot error"));
|
|
return false;
|
|
}
|
|
}
|
|
// Verify the CVI slot subscriptions.
|
|
std::sort(begin(), end(), HexagonInstr::lessCVI);
|
|
// create vector of hvx instructions to check
|
|
HVXInstsT hvxInsts;
|
|
hvxInsts.clear();
|
|
for (iterator I = begin(); I != end(); ++I) {
|
|
struct CVIUnits inst;
|
|
inst.Units = I->CVI.getUnits();
|
|
inst.Lanes = I->CVI.getLanes();
|
|
if (inst.Units == 0)
|
|
continue; // not an hvx inst or an hvx inst that doesn't uses any pipes
|
|
hvxInsts.push_back(inst);
|
|
}
|
|
// if there are any hvx instructions in this packet, check pipe usage
|
|
if (hvxInsts.size() > 0) {
|
|
unsigned startIdx, usedUnits;
|
|
startIdx = usedUnits = 0x0;
|
|
if (checkHVXPipes(hvxInsts, startIdx, usedUnits) == false) {
|
|
// too many pipes used to be valid
|
|
reportError(llvm::Twine("invalid instruction packet: slot error"));
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool HexagonShuffler::shuffle() {
|
|
if (size() > HEXAGON_PACKET_SIZE) {
|
|
// Ignore a packet with with more than what a packet can hold
|
|
// or with compound or duplex insns for now.
|
|
reportError(llvm::Twine("invalid instruction packet"));
|
|
return false;
|
|
}
|
|
|
|
// Check and prepare packet.
|
|
bool Ok = true;
|
|
if (size() > 1 && (Ok = check()))
|
|
// Reorder the handles for each slot.
|
|
for (unsigned nSlot = 0, emptySlots = 0; nSlot < HEXAGON_PACKET_SIZE;
|
|
++nSlot) {
|
|
iterator ISJ, ISK;
|
|
unsigned slotSkip, slotWeight;
|
|
|
|
// Prioritize the handles considering their restrictions.
|
|
for (ISJ = ISK = Packet.begin(), slotSkip = slotWeight = 0;
|
|
ISK != Packet.end(); ++ISK, ++slotSkip)
|
|
if (slotSkip < nSlot - emptySlots)
|
|
// Note which handle to begin at.
|
|
++ISJ;
|
|
else
|
|
// Calculate the weight of the slot.
|
|
slotWeight += ISK->Core.setWeight(HEXAGON_PACKET_SIZE - nSlot - 1);
|
|
|
|
if (slotWeight)
|
|
// Sort the packet, favoring source order,
|
|
// beginning after the previous slot.
|
|
std::sort(ISJ, Packet.end());
|
|
else
|
|
// Skip unused slot.
|
|
++emptySlots;
|
|
}
|
|
|
|
for (iterator ISJ = begin(); ISJ != end(); ++ISJ)
|
|
DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) {
|
|
dbgs() << '/';
|
|
dbgs().write_hex(ISJ->CVI.getUnits()) << '|';
|
|
dbgs() << ISJ->CVI.getLanes();
|
|
} dbgs() << ':'
|
|
<< HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode();
|
|
dbgs() << '\n');
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
return Ok;
|
|
}
|
|
|
|
void HexagonShuffler::reportError(llvm::Twine const &Msg) {
|
|
if (ReportErrors)
|
|
Context.reportError(Loc, Msg);
|
|
}
|