llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

92 lines
3.2 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_usubo_s32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_usubo_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBO1]](s1)
; CHECK: $vgpr0 = COPY [[USUBO]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
%4:_(s32) = G_ZEXT %3
$vgpr0 = COPY %2
$vgpr1 = COPY %4
...
---
name: test_usubo_s7
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_usubo_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1
%4:_(s7), %5:_(s1) = G_USUBO %2, %3
%6:_(s32) = G_ZEXT %4
%7:_(s32) = G_ZEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
...
---
name: test_usubo_s16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_usubo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1
%4:_(s16), %5:_(s1) = G_USUBO %2, %3
%6:_(s32) = G_ZEXT %4
%7:_(s32) = G_ZEXT %5
$vgpr0 = COPY %6
$vgpr1 = COPY %7
...