forked from OSchip/llvm-project
78 lines
3.5 KiB
TableGen
78 lines
3.5 KiB
TableGen
//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'A', Atomic
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// Instructions extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1),
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opcodestr, "$rd, (${rs1})"> {
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let rs2 = 0;
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}
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multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : LR_r<0, 0, funct3, opcodestr>;
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def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs2, (${rs1})">;
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multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
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defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
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defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
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defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
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defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
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defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
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defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
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defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
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defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
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defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
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defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
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} // Predicates = [HasStdExtA]
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let Predicates = [HasStdExtA, IsRV64] in {
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defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
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defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
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defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
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defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
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defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
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defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
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defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
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defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
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} // Predicates = [HasStedExtA, IsRV64]
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