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llvm-project/llvm/lib/Target/RISCV/MCTargetDesc
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Alex Bradbury b22f751fa7 Thread MCSubtargetInfo through Target::createMCAsmBackend 
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. 
D20830 threaded an MCSubtargetInfo reference through 
MCAsmBackend::relaxInstruction, but this isn't the only function that would 
benefit from access. This patch removes the Triple and CPUString arguments 
from createMCAsmBackend and replaces them with MCSubtargetInfo.

This patch just changes the interface without making any intentional 
functional changes. Once in, several cleanups are possible:
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)

This change initially exposed PR35686, which has since been resolved in r321026.

Differential Revision: https://reviews.llvm.org/D41349

llvm-svn: 321692
 		2018-01-03 08:53:05 +00:00
..
CMakeLists.txt [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
LLVMBuild.txt [RISCV] Add RISCVInstPrinter and basic MC assembler tests 2017-08-15 13:08:29 +00:00
RISCVAsmBackend.cpp Thread MCSubtargetInfo through Target::createMCAsmBackend 2018-01-03 08:53:05 +00:00
RISCVBaseInfo.h [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVELFObjectWriter.cpp [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
RISCVFixupKinds.h [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
RISCVMCAsmInfo.cpp Distinguish between code pointer size and DataLayout::getPointerSize() in DWARF info generation 2017-04-17 17:41:25 +00:00
RISCVMCAsmInfo.h
…
RISCVMCCodeEmitter.cpp [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
RISCVMCExpr.cpp [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVMCExpr.h [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVMCTargetDesc.cpp [RISCV] Prepare for the use of variable-sized register classes 2017-10-19 14:29:03 +00:00
RISCVMCTargetDesc.h Thread MCSubtargetInfo through Target::createMCAsmBackend 2018-01-03 08:53:05 +00:00