maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Ana Pazos e3d248361e [RISCV] Pass MCSubtargetInfo to print methods. 
Summary:

This change allows checking for ISA extensions in print methods.

Reviewers: asb, niosHD

Reviewed By: asb, niosHD

Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal

Differential Revision: https://reviews.llvm.org/D41503

llvm-svn: 322345
 		2018-01-12 02:27:00 +00:00
..
AsmParser [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 2017-12-15 10:20:51 +00:00
Disassembler [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention 2017-12-13 09:57:25 +00:00
InstPrinter [RISCV] Pass MCSubtargetInfo to print methods. 2018-01-12 02:27:00 +00:00
MCTargetDesc Thread MCSubtargetInfo through Target::createMCAsmBackend 2018-01-03 08:53:05 +00:00
TargetInfo Fix RISCV build after r318352 2017-11-16 18:39:31 +00:00
CMakeLists.txt [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
LLVMBuild.txt [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00
RISCV.h [RISCV] Codegen support for memory operations on global addresses 2017-11-08 13:24:21 +00:00
RISCV.td [RISCV] Pass MCSubtargetInfo to print methods. 2018-01-12 02:27:00 +00:00
RISCVAsmPrinter.cpp [RISCV] Add basic support for inline asm constraints 2018-01-10 20:05:09 +00:00
RISCVCallingConv.td [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp [RISCV] Reserve an emergency spill slot for the register scavenger when necessary 2018-01-11 11:17:19 +00:00
RISCVFrameLowering.h [RISCV] Reserve an emergency spill slot for the register scavenger when necessary 2018-01-11 11:17:19 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Add basic support for inline asm constraints 2018-01-10 20:05:09 +00:00
RISCVISelLowering.cpp [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics 2018-01-10 20:12:00 +00:00
RISCVISelLowering.h [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics 2018-01-10 20:12:00 +00:00
RISCVInstrFormats.td [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVInstrFormatsC.td [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
RISCVInstrInfo.h [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
RISCVInstrInfo.td [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools 2017-12-13 12:46:55 +00:00
RISCVInstrInfoA.td [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
RISCVInstrInfoC.td [RISCV] Add Defs Uses information for c.jal and c.addi4spn 2018-01-02 12:09:29 +00:00
RISCVInstrInfoD.td [RISCV] Implement floating point assembler pseudo instructions 2017-12-13 11:37:19 +00:00
RISCVInstrInfoF.td [RISCV] Implement floating point assembler pseudo instructions 2017-12-13 11:37:19 +00:00
RISCVInstrInfoM.td [RISCV] MC layer support for the standard RV64M instruction set extension 2017-12-07 10:56:07 +00:00
RISCVMCInstLower.cpp [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
RISCVMachineFunctionInfo.h [RISCV] Support for varargs 2018-01-10 19:41:03 +00:00
RISCVRegisterInfo.cpp [RISCV] Support stack frames and offsets up to 32-bits 2018-01-10 19:53:46 +00:00
RISCVRegisterInfo.h [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
RISCVRegisterInfo.td [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
RISCVSubtarget.cpp [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00
RISCVSubtarget.h [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVTargetMachine.cpp [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
RISCVTargetMachine.h [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00